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telephony controller. P83CL882 Datasheet |
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INTEGRATED CIRCUITS
DATA SHEET
P83CL882
80C51 Ultra Low Power (ULP)
telephony controller
Product specification
File under Integrated Circuits, IC22
2001 Jun 19
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Philips Semiconductors
80C51 Ultra Low Power (ULP) telephony controller
Product specification
P83CL882
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING INFORMATION
5.1 Pin configuration
5.2 Pin description
6 FUNCTIONAL DESCRIPTION
6.1 Oscillator circuitry
6.2 The CPU
6.3 Interrupt controller
6.4 Port control logic
6.5 Timer 0 and Timer 1 event counters
6.6 Timer 2
6.7 Watchdog Timer
6.8 I2C-bus serial I/O (master/slave interface)
6.9 MSK modem
6.10 Internal Data Memory
6.11 Special Function Registers overview
7 INSTRUCTION SET
7.1 Instruction map
8 APPLICATION INFORMATION
8.1 Introduction
8.2 Differences between P83CL882 and the
Metalink EH emulation system
8.3 The asynchronous handshake CPU
9 HOW TO ESTIMATE P83CL882 POWER
CONSUMPTION
9.1 General
9.2 Modes
9.3 Examples of power consumption estimation
10 LIMITING VALUES
11 CHARACTERISTICS
12 PACKAGE OUTLINE
13 SOLDERING
13.1 Introduction to soldering surface mount
packages
13.2 Reflow soldering
13.3 Wave soldering
13.4 Manual soldering
13.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
14 DATA SHEET STATUS
15 DEFINITIONS
16 DISCLAIMERS
17 PURCHASE OF PHILIPS I2C COMPONENTS
2001 Jun 19
2
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Philips Semiconductors
80C51 Ultra Low Power (ULP) telephony controller
Product specification
P83CL882
1 FEATURES
• Full static asynchronous handshake 80C51 CPU;
enhanced 8-bit architecture with:
– Standard 80C51 instruction set
– CPU speed independent of clock frequency, average
speed: 4.8 Mips at 3.0 V
– Non-page oriented instructions
– Direct addressing
– Four 8-byte RAM register banks
– Stack depth limited only by available internal RAM
(maximum 128 bytes)
– Multiply, divide, subtract and compare instructions.
• 17 source, 17 vector interrupt structure with two priority
levels, polarity and sensitivity choice
• 24 general purpose I/O pins
• Timer 0 and 1: two standard 16-bit timer/event counters
• Timer 2: 16-bit timer/event counter with capture,
compare and auto-reload function
• Watchdog Timer
• Wake-up counter
• Idle and Power-down modes
• 4-kbyte ROM: mask programmed read only memory
• Supply voltage: 1.8 to 3.6 V
• 128 bytes RAM
• Internal crystal oscillator
• Reset I/O pin for external reset from master or to slave
• MSK modem including Manchester encoder/decoder
with 2 digital outputs (by SW) for analog cordless
telephones (standards CT0/CT1/CT1+)
• I2C-bus master/slave (transmitter/receiver, maximum
frequency 400 kHz).
2 GENERAL DESCRIPTION
The P83CL882 is manufactured in an advanced CMOS
technology. The P83CL882 is a member of the VTELX
family of low-power, low-voltage 80CL51 microcontrollers
with advanced features for telecom applications. The
Philips exclusive, asynchronous handshaking technology
has been used for the CPU implementation which makes
the CPU to run at its maximum speed independent of the
used crystal frequency.
The P83CL882 is especially suited for low cost analog
cordless telephone applications (CT0, CT1 and CT1+
standards) and wired feature phones. For this purpose,
functions like MSK modem and I2C-bus are integrated
on-chip.
The device is optimized for low-power consumption. It has
two software selectable modes for power reduction: Idle
and Power-down. In addition, the clock to all unused
peripheral blocks can be switched off.
The instruction set is based on that of the 80C51. The
P83CL882 also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities. The instruction set consists of
over 100 instructions: 49 one-byte, 46 two-byte, and
16 three-byte. Port 2 is not incorporated, therefore there is
no external data or memory access and the MOVX
operations cannot be used.
3 ORDERING INFORMATION
TYPE NUMBER
P83CL882T/xxx
NAME
TSSOP32
PACKAGE
DESCRIPTION
plastic thin shrink small outline package; 32 leads;
body width 6.1 mm
VERSION
SOT487-1
2001 Jun 19
3
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