extended memory. P87C51MB2 Datasheet

P87C51MB2 memory. Datasheet pdf. Equivalent

Part P87C51MB2
Description 80C51 8-bit microcontroller family with extended memory
Feature P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended memory; 64 kB/96 kB OTP with 2.
Manufacture NXP
Datasheet
Download P87C51MB2 Datasheet



P87C51MB2
P87C51MB2/P87C51MC2
80C51 8-bit microcontroller family with extended memory;
64 kB/96 kB OTP with 2 kB/3 kB RAM
Rev. 03 — 13 November 2003
Product data
1. General description
The P87C51Mx2 represents the first microcontroller based on Philips
Semiconductors’ new 51MX core. The P87C51MC2 features 96 kbytes of OTP
program memory and 3 kbytes of data SRAM, while the P87C51MB2 has 64 kbytes
of OTP and 2 kbytes of RAM. In addition, both devices are equipped with a
Programmable Counter Array (PCA), a watchdog timer that can be configured to
different time ranges through SFR bits, as well as two enhanced UARTs and Serial
Peripheral Interface (SPI).
Philips Semiconductors’ 51MX (Memory eXtension) core is an accelerated 80C51
architecture that executes instructions at twice the rate of standard 80C51 devices.
The linear address range of the 51MX has been expanded to support up to 8 Mbytes
of program memory and 8 Mbytes of data memory. It retains full program code
compatibility to enable design engineers to re-use 80C51 development tools,
eliminating the need to move to a new, unfamiliar architecture. The 51MX core also
retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced
peripherals and Application Specific Integrated Circuits (ASICs).
The P87C51Mx2 provides greater functionality, increased performance and overall
lower system cost. By offering an embedded memory solution combined with the
enhancements to manage the memory extension, the P87C51Mx2 eliminates the
need for software work-around. The increased program memory enables design
engineers to develop more complex programs in a high-level language like C, for
example, without struggling to contain the program within the traditional 64 kbytes of
program memory. These enhancements also greatly improve C Language efficiency
for code size below 64 kbytes.
The 51MX core is described in more detail in the 51MX Architecture Reference.
2. Features
2.1 Key features
s Extended features of the 51MX Core:
x 23-bit program memory space and 23-bit data memory space
x Linear program and data address range expanded to support up to 8 Mbytes
each
x Program counter expanded to 23 bits
x Stack pointer extended to 16 bits enabling stack space beyond the 80C51
limitation



P87C51MB2
Philips Semiconductors
P87C51MB2/P87C51MC2
80C51 8-bit microcontroller family
9397 750 12302
Product data
x New 23-bit extended data pointer and two 24-bit universal pointers greatly
improve C compiler code efficiency in using pointers to access variables in
different spaces
s 100% binary compatibility with the classic 80C51 so that existing code is
completely reusable
s Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
s 96 kbytes (MC2) or 64 kbytes (MB2) of on-chip OTP
s 3 kbytes (MC2) or 2 kbytes (MB2) of on-chip RAM
s Programmable Counter Array (PCA)
s Two full-duplex enhanced UARTs and Serial Peripheral Interface (SPI)
communication modules
2.2 Key benefits
s Increases program/data address range to 8 Mbytes each
s Enhances performance and efficiency for C programs
s Fully 80C51-compatible microcontroller
s Provides seamless and compelling upgrade path from classic 80C51
s Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs
s Supported by wide range of 80C51 development systems and programming tools
vendors
s The P87C51Mx2 makes it possible to develop applications at lower cost and with
a reduced time-to-market
2.3 Complete features
s Fully static
s Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
s 96 kbytes or 64 kbytes of on-chip OTP
s 3 kbytes or 2 kbytes of on-chip RAM
s 23-bit program memory space and 23-bit data memory space
s Four-level interrupt priority
s 34 I/O lines (5 ports)
s Three Timers: Timer0, Timer1 and Timer2
s Two full-duplex enhanced UARTs with baud rate generator
s Framing error detection
s Automatic address recognition
s Supports industry-standard Serial Peripheral Interface (SPI) with a baud rate up to
6 Mbits/s
s Power control modes
s Clock can be stopped and resumed
s Idle mode
s Power down mode with advanced clock control
s Second DPTR register
s Asynchronous port reset
s Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five
Capture/Compare modules
Rev. 03 — 13 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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