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SN54LS113A

Motorola Inc
Part Number SN54LS113A
Manufacturer Motorola Inc
Description DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Published Apr 16, 2005
Detailed Description SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock input...
Datasheet PDF File SN54LS113A PDF File

SN54LS113A
SN54LS113A

Overview
SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs.
These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted.
The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup times are observed.
Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 1 Q 5(9) 6(8) Q SET (SD) 4(10) J ...


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