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DECODER/ DEMULTIPLEXER. SN54LS156 Datasheet |
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DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4
Decoder/Demultiplexers. These devices have two decoders with common
2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an
Enable gate with one active HIGH and one active LOW input. Decoder “b” has
two active LOW Enable inputs. If the Enable functions are satisfied, one
output of each decoder will be LOW as selected by the address inputs. The
LS156 has open collector outputs for wired-OR (DOT-AND) decoding and
function generator applications.
The LS155 and LS156 are fabricated with the Schottky barrier diode
process for high speed and are completely compatible with all Motorola TTL
families.
• Schottky Process for High Speed
• Multifunction Capability
• Common Address Inputs
• True or Complement Data Demultiplexing
• Input Clamp Diodes Limit High Speed Termination Effects
• ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Eb Eb A0 O3b O2b O1b O0b
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56
78
Ea Ea A1 O3a O2a O1a O0a GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
A0, A1
Ea, Eb
Ea
O0 – O3
Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges. The HIGH level drive for the LS156 must be established by an external
resistor.
SN54/74LS155
SN54/74LS156
DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
LS156-OPEN-COLLECTOR
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
1 2 13 3 14 15
E
DECODER a
012
A0
A1
3
A0 E
A1 DECODER b
0 123
765 4
9 10 11 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-262
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LOGIC DIAGRAM
SN54/74LS155 • SN54/74LS156
Ea Ea
12
A0 A1
13 3
Eb Eb
14 15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
7 6 5 4 9 10 11 12
O0a O1a O2a O3a O0b O1b O2b O3b
FUNCTIONAL DESCRIPTION
The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti-
plexers with common Address inputs and separate gated
Enable inputs. When enabled, each decoder section accepts
the binary weighted Address inputs (A0, A1) and provides four
mutually exclusive active LOW outputs (O0 – O3). If the Enable
requirements of each decoder are not met, all outputs of that
decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (Ea•Ea). In demultiplexing applica-
tions, Decoder “a” can accept either true or complemented
data by using the Ea or Ea inputs respectively. The enable gate
for Decoder “b” requires two active LOW inputs (Eb•Eb). The
LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti-
plexer by tying Ea to Eb and relabeling the common connection
as (A2). The other Eb and Ea are connected together to form
the common enable.
The LS155 and LS156 can be used to generate all four
minterms of two variables. These four minterms are useful in
some applications replacing multiple gate functions as shown
in Fig. a. The LS156 has the further advantage of being able to
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅
(E + A0 + A1)
where E = Ea + Ea; E = Eb + Eb
EE
A0 O0 A0
A1 A1
EE
A0 O1 A0
A1 A1
EE
A0 O2 A0
A1 A1
EE
A0 O3 A0
A1 A1
O0
O1
O2
O3
Figure a
TRUTH TABLE
ADDRESS ENABLE “a”
OUTPUT “a”
ENABLE “b”
OUTPUT “b”
A0 A1 Ea Ea O0 O1 O2 O3 Eb Eb O0 O1 O2 O3
X X L X H H HH H X H H H H
X X X H H H HH X H H H H H
L L H L L H HH L L L H H H
H L H L H L HH L L H L H H
L H H L H H LH L L H H L H
H H H L H H HL L L H H H L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
FAST AND LS TTL DATA
5-263
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SN54 / 74LS155
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
VIH
Parameter
Input HIGH Voltage
Limits
Min Typ Max
2.0
Unit Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
54
VIL Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5
2.5 3.5
2.7 3.5
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
10
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C)
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Propagation Delay
Address, Ea or Eb to Output
Propagation Delay
Address to Output
Propagation Delay
Ea to Output
Limits
Min Typ Max
10 15
19 30
17 26
19 30
18 27
18 27
Unit
ns
ns
ns
Test Conditions
Figure 1
Figure 2
Figure 1
VCC = 5.0 V
CL = 15 pF
AC WAVEFORMS
VIN
VOUT
1.3 V
tPHL
1.3 V
1.3 V
tPLH
1.3 V
Figure 1
VIN
VOUT
1.3 V
tPHL
1.3 V
1.3 V
tPLH
1.3 V
Figure 2
FAST AND LS TTL DATA
5-264
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