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D FLIP-FLOP. SN54LS174 Datasheet |
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HEX D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Asynchronous Common Reset
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q5 D5 D4 Q4 D3 Q3 CP
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56 78
MR Q0 D0 D1 Q1 D2 Q2 GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
D0 – D5
CP
MR
Q0 – Q5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
MR CP D5 D4 D3
D2 D1
D0
1 9 14
13
11
6
43
DQ
CPCD
VCC = PIN 16
GND = PIN 8
15
Q5
= PIN NUMBERS
DQ
CPCD
DQ
CPCD
12 10
Q4 Q3
DQ
CPCD
7
Q2
DQ
CPCD
5
Q1
DQ
CPCD
2
Q0
SN54/74LS174
HEX D FLIP-FLOP
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
3 4 6 11 13 14
D0 D1 D2 D3 D4 D5
9 CP
1 MR
Q0 Q1 Q2 Q3 Q4 Q5
2 5 7 10 12 15
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-1
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SN54 / 74LS174
FUNCTIONAL DESCRIPTION
The LS174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Master
Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding flip-
flop’s output following the LOW to HIGH Clock (CP) transition.
A LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The LS174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
DQ
H
L
Note 1: t = n + 1 indicates conditions after next clock.
H
L
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
54
VIL Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5
2.5 3.5
2.7 3.5
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
26 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-2
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SN54 / 74LS174
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPHL
tPLH
tPHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
th
trec
Parameter
Clock or MR Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max
30 40
23 35
20 30
21 30
Unit
MHz
ns
ns
Limits
Min Typ Max
20
20
5.0
25
Unit
ns
ns
ns
ns
AC WAVEFORMS
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
1/fmax
tw
CP 1.3 V
1.3 V
ts(H) th(H)ts(L) th(L)
D*
Q
1.3 V 1.3 V
tPLH
1.3 V
1.3 V
tPHL
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
tW
MR 1.3 V 1.3 V
trec
1.3 V
CP
Q tPHL
1.3 V 1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
FAST AND LS TTL DATA
5-3
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