SHIFT REGISTER. SN54LS195A Datasheet

SN54LS195A REGISTER. Datasheet pdf. Equivalent

SN54LS195A Datasheet
Recommendation SN54LS195A Datasheet
Part SN54LS195A
Description UNIVERSAL 4-BIT SHIFT REGISTER
Feature SN54LS195A; SN54/74LS195A UNIVERSAL 4-BIT SHIFT REGISTER The SN54 / 74LS195A is a high speed 4-Bit Shift Registe.
Manufacture Motorola Inc
Datasheet
Download SN54LS195A Datasheet




Motorola  Inc SN54LS195A
UNIVERSAL 4-BIT
SHIFT REGISTER
The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical
shift frequencies of 39 MHz. It is useful for a wide variety of register and
counting applications. It utilizes the Schottky diode clamped process to
achieve high speeds and is fully compatible with all Motorola TTL products.
Typical Shift Right Frequency of 39 MHz
Asynchronous Master Reset
J, K Inputs to First Stage
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q0 Q1 Q2 Q3 Q3 CP PE
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
12
MR J
3 4 56 78
K P0 P1 P2 P3 GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
PE
P0 – P3
J
K
CP
MR
Q0 – Q3
Q3
Parallel Enable (Active LOW) Input
Parallel Data Inputs
First Stage J (Active HIGH) Input
First Stage K (Active LOW) Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs (Note b)
Complementary Last Stage Output (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS195A
UNIVERSAL 4-BIT
SHIFT REGISTER
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
9456 7
2 J PE P0 P1 P2 P3
10 CP
Q3 11
3 K MR Q0 Q1 Q2 Q3
1 15 14 13 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-366



Motorola  Inc SN54LS195A
LOGIC DIAGRAM
PE J K P0
923
4
SN54 / 74LS195A
P1
5
P2
6
P3
7
MR CP
1 10
R CD Q0
CP
S Q0
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
15
Q0
R CD
CP
S Q0
14
Q1
R CD
CP
S Q2
13
Q2
R CD Q3
CP
S Q3
12 11
Q3 Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS195A 4-Bit Shift Register. The device
is useful in a wide variety of shifting, counting and storage
applications. It performs serial, parallel, serial to parallel, or
parallel to serial data transfers at very high speeds.
The LS195A has two primary modes of operation, shift right
(Q0 Q1) and parallel load which are controlled by the state of
the Parallel Enable (PE) input. When the PE input is HIGH,
serial data enters the first flip-flop Q0 via the J and K inputs and
is shifted one bit in the direction Q0 Q1 Q2 Q3 following
each LOW to HIGH clock transition. The JK inputs provide the
flexibility of the JK type input for special applications, and the
simple D type input for general applications by tying the two
pins together. When the PE input is LOW, the LS195A appears
as four common clocked D flip-flops. The data on the parallel
inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,
Q2, Q3 outputs following the LOW to HIGH clock transition.
Shift left operations (Q3 Q2) can be achieved by tying the Qn
Outputs to the Pn–1 inputs and holding the PE input LOW.
All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since the
LS195A utilizes edge-triggering, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operation —
except for the set-up and release time requirements.
A LOW on the asynchronous Master Reset (MR) input sets
all Q outputs LOW, independent of any other input condition.
MODE SELECT — TRUTH TABLE
OPERATING MODES
Asynchronous Reset
INPUTS
OUTPUTS
MR PE J K Pn Q0 Q1 Q2 Q3 Q3
L X XXX L L L L H
Shift, Set First Stage
H h h h X H q0 q1 q2 q2
Shift, Reset First
H h I I X L q0 q1 q2 q2
Shift, Toggle First Stage H h h I X q0 q0 q1 q2 q2
Shift, Retain First Stage H h I h X q0 q0 q1 q2 q2
Parallel Load
H I X X pn p0 p1 p2 p3 p3
L = LOW voltage levels
H = HIGH voltage levels
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to
HIGH clock transition.
FAST AND LS TTL DATA
5-367



Motorola  Inc SN54LS195A
SN54 / 74LS195A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC
Supply Voltage
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
TA Operating Ambient Temperature Range
54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High
IOL Output Current — Low
54, 74
54
74
– 0.4
4.0
8.0
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
– 0.65 – 1.5
V VCC = MIN, IIN = – 18 mA
Output HIGH Voltage
54 2.5 3.5
74 2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
IIH Input HIGH Current
20
0.1
IIL Input LOW Current
– 0.4
IOS Short Circuit Current (Note 1) – 20
– 100
ICC Power Supply Current
21
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol
Parameter
Min Typ Max
fMAX
Maximum Clock Frequency
30 39
tPLH
tPHL
Propagation Delay,
Clock to Output
14 22
17 26
tPHL
Propagation Delay,
MR to Output
19 30
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
mA VCC = MAX
mA VCC = MAX
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
ts
ts
trec
trel
th
Parameter
CP Clock Pulse Width
MR Pulse Width
PE Setup Time
Data Setup Time
Recovery Time
PE Release Time
Data Hold Time
Limits
Min Typ Max
16
12
25
15
25
10
0
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-368







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