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8-bit microcontroller. P87C552 Datasheet |
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INTEGRATED CIRCUITS
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, low voltage (2.7 V to 5.5 V),
low power
Product data
Supersedes data of 1999 Mar 30
2003 Apr 01
Philips
Semiconductors
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Philips Semiconductors
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, low voltage (2.7 V to 5.5 V), low power
Product data
P87C552
DESCRIPTION
The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C552 has the same instruction set as
the 80C51.
The 87C552 contains a 8k × 8 non-volatile EPROM, a 256 × 8
read/write data memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, four-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I2C-bus), a “watchdog” timer and on-chip
oscillator and timing circuits. For systems that require extra
capability, the 8xC552 can be expanded using standard TTL
compatible memories and logic.
In addition, the 8xC552 has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. Optionally, the ADC can be operated
in Idle mode. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions:
49 one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal,
58% of the instructions are executed in 0.75µs and 40% in 1.5µs.
Multiply and divide instructions require 3µs.
FEATURES
• 80C51 central processing unit
• 8k × 8 EPROM expandable externally to 64k bytes
• An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
• Two standard 16-bit timer/counters
• 256 × 8 RAM, expandable externally to 64k bytes
• Capable of producing eight synchronized, timed outputs
• A 10-bit ADC with eight multiplexed analog inputs
• Fast 8-bit ADC option
• Two 8-bit resolution, pulse width modulation outputs
• Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
• I2C-bus serial I/O port with byte oriented master and slave
functions
• On-chip watchdog timer
• Extended temperature ranges
• Full static operation – 0 to 16 MHz
• Operating voltage range: 2.7V to 5.5V (0 to 16MHz)
• Security bits:
– OTP/EPROM – 3 bits
• Encryption array – 64 bytes
• 4 level priority interrupt
• 15 interrupt sources
• Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
• Power control modes
– Clock can be stopped and resumed
– Idle mode
– Power down mode
• Second DPTR register
• ALE inhibit for EMI reduction
• Programmable I/O pins
• Wake-up from power-down by external interrupts
• Software reset
• Power-on detect reset
• ADC charge pump disable
• ONCE mode
• ADC active in Idle mode
2003 Apr 01
2 853-2410 29338
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