Analog Circuit. PAC80 Datasheet

PAC80 Circuit. Datasheet pdf. Equivalent

Part PAC80
Description In-System Programmable Analog Circuit
Feature ispPAC 80 TM In-System Programmable Analog Circuit Features • IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG .
Manufacture Lattice Semiconductor
Datasheet
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ispPAC 80 TM In-System Programmable Analog Circuit Features PAC80 Datasheet
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PAC80
ispPAC 80TM
In-System Programmable Analog Circuit
Features
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG
— Instrument Amplifier Gain Stage
— Precision Active Filtering (50kHz to 500kHz)
— Continuous-Time Fifth Order Low Pass Topology
— Dual, A/B Configuration Memory
— Non-Volatile E2CMOS Cells
— IEEE 1149.1 JTAG Serial Port Programming
• UNIQUE FLEXIBILITY AND PERFORMANCE
— Programmable Gain Range (0dB to 20dB)
— Implements Multiple Filter Types: Elliptical,
Chebyshev, Bessel, Butterworth, Linear Phase,
Gaussian and Legendre
— Low Distortion (THD < -74dB max @ 100kHz)
— Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL I/O
— High CMR (58dB) Instrument Amplifier Input
— 2.5V Common Mode Reference on Chip
— Rail-to-Rail Voltage Outputs
• SINGLE SUPPLY 5V OPERATION
— Power Dissipation of 165mW
— 16-Pin Plastic SOIC, PDIP Packages
• APPLICATIONS INCLUDE INTEGRATED
— Single +5V Supply Signal Conditioning
— Programmable Filters With Fully Differential I/O
— Analog Front Ends, 12-Bit Data Acq. Systems
— DSP System Front End Signal Conditioning
— High-Performance Reconstruction Filters
Typical Application Diagram
5V 5V
ispPAC80
Vin
12-Bit Differential
Input ADC
Ain+
Ain-
A/B & Gain
SPI Control
VREFout
Reference
5V
DSP
Functional Block Diagram
TMS 1
TCK 2
TDI 3
TDO 4
CS 5
CAL 6
ENSPI 7
GND 8
IA OA
5th Order LPF
E2CMOS Cfg A E2CMOS Cfg B
Ref & Auto-Cal
ISP Control
16 VS
15 TEST
14 OUT+
13 OUT
12 TEST
11 IN+
10 IN
9 VREFOUT
ispPAC80
Description
The ispPAC80 is a member of the Lattice family of In-System
Programmable analog circuits, digitally configured via non-
volatile E2CMOS® technology.
Analog building blocks, called PACell™(s), replace traditional
analog components such as opamps, eliminating the need for
external resistors and capacitors. With no requirement for
external configuration components, ispPAC80 expedites the
design process, simplifying prototype circuit implementation
and change, while providing high-performance integrated func-
tionality. With all components on chip, there is no longer a
concern of performance degradation due to component mis-
match or other external factors. The ispPAC80 provides reliable
and repeatable performance, every time.
Designers configure the ispPAC80 and verify its performance
using PAC-Designer™, an easy to use, Microsoft Windows®
compatible program. A filter configuration database is provided
whereby thousands of different configurations can be realized.
No special understanding of filter synthesis is required beyond
that of general specifications such as corner frequency and
stopband attenuation, etc. The software lists the possible
choices that meet the designer’s specifications which can then
be loaded directly into either of two device
(A/B) configurations from the lookup table. Device program-
ming is supported using PC parallel port I/O operations.
The ispPAC80 is configured through its IEEE Standard 1149.1
compliant serial port. The flexible In-System Programming
capability enables programming, verification and reconfig-
uration, if desired, directly on the printed circuit board.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com
March 2000
pac80_03
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PAC80
Specifications ispPAC80
TA = 25°C; VS = 5.0V; 1V < VOUT < 4V; Gain = 1; Output load = 200pF, 1M. Filter configuration = CC051042, FP = 50kHz;
Auto-Cal initiated immediately prior. (Unless otherwise specified).
DC Electrical Characteristics
Symbol
Parameter
Condition
Analog Input
VIN± (1)
VIN-DIFF
VOS (2)
Input Voltage Range
Differential Input Voltage Swing (2)
Differential Offset Voltage (Input Referred)
Applied to Either VIN+ or VIN-
2| VIN+ VIN-|
G = 10
G=1
VOS/T
RIN
CIN
IB
eN
Analog Output
Differential Offset Voltage Drift
Input Resistance
Input Capacitance
Input Bias Current
Input Noise Voltage Density
-40 to +85°C
at DC
At 10kHz, Referred to Input, G = 10
VOUT±
Output Voltage Range
VOUT-DIFF
Differential Output Voltage Swing (2)
IOUT±
Output Current
VCM Common Mode Output Voltage
Static Performance
Present at Either VOUT+ or VOUT
2| VOUT+ VOUT|
Source/Sink
(VOUT+ + VOUT-)/2
G
Programmable Gain Range
Input Gain Amplifier (1, 2, 5, 10)
G/∆T
Gain Error
Gain Drift
RL = 300Differential
-40 to +85°C
PSR
Power Supply Rejection
Differential at 1kHz
Single-ended at 1kHz
Common Mode Reference Output (VREFOUT)
VREFOUT
Reference Output Voltage Range
Reference Output Voltage Drift
Nominally 2.500V
-40 to +85°C
IREFOUT
Reference Output Current
Reference Output Noise Voltage
(VREFOUT = ±1%) Source
(VREFOUT = ±1%) Sink
10MHz Bandwidth
Reference Power Supply Rejection
1kHz
Programming
Erase/Reprogram Cycles
Digital I/O
VIL
VIH
IIL, IIH
Input Low Voltage
Input High Voltage
Input Leakage Current
0VTCK,ENSPI,CAL Input VS
0VTDI,TMS,CSb Inputs VS
VOL Output Low Voltage (TDO)
VOH Output High Voltage (TDO)
IOL = 4.0mA
IOH = -1.0mA
Min.
1
6
0.1
9.6
10
2.495
0
-0.2
10K
0
2
2.4
Typ.
30
0.3
40
109
2
1
80
2.5
0.5
20
80
70
50
50
350
40
80
1M
Max.
Units
4V
Vp-p
200 µV
2 mV
µV/°C
pF
pA
nV/Hz
4.9
2.505
V
Vp-p
mA
V
20 dB
2.5 %
ppm/°C
dB
dB
0.2 %
ppm/°C
µA
µA
µVRMS
dB
cycles
0.8
VS
-10/+40
-70/+10
0.5
V
V
µA
µA
V
V
2





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