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COMPANION CIRCUIT. PACVGA200 Datasheet |
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CALIFORNIA MICRO DEVICES
PACVGA200
VGA PORT COMPANION CIRCUIT
Features
7 channels of ESD protection for all VGA port
connector pins meeting IEC-61000-4-2 Level-4 ESD
requirements (8KV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
75 Ω termination resistors for VIDEO lines (matched
to 1% typ.)
Bi-directional level shifting N-channel FETs provided for
DDC_CLK & DDC_DATA channels
Compact 24-pin QSOP package
Pin Diagram
Product Description
24-PIN QSOP PACKAGE
The PACVGA200 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-1000-4-
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage
Video Controller ICs and provide design flexibility in multi-supply-voltage environments.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC4. These
drivers have nominal 60Ω output impedance to match the characteristic impedance of the HSYNC & VSYNC lines of the video
cables typically used in PC applications.
Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage
than the monitor.
Three 75Ω termination resistors suitable for terminating the video signals from the video DAC are also provided. These
resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and
the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching for the R/G/B
signals.
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current
from the VCC3 supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.
An internal diode (D1 in schematic below) is also provided so that VCC3 can be derived from VCC4, if desired, by connecting VCC3
to V_BIAS. In applications where VCC4 may be powered down, diode D1 blocks any DC current paths from the DDC_OUT pins
back to the powered down VCC4 rail via the top ESD protection diodes.
Schematic Diagram
© 2000 California Micro Devices Corp. All rights reserved. PACVGA200 is a trademark of California Micro Devices Corp.
4/00 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
C0641299
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CALIFORNIA MICRO DEVICES
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
VCC1, VCC2 , VCC3 & VCC4 supply voltage
Diode D1 forward current
GND-0.5, +6.0
100
DC voltage at inputs:
VIDEO_1, VIDEO_2, VIDEO_3
TERM_1, TERM_2, TERM_3
GND-0.5, VCC1+0.5
-6.0, +6.0
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
Temperature:
GND-0.5, VCC2+0.5
GND-0.5, VCC3+0.5
GND-0.5, VCC4+0.5
Storage
-40 to +150
Operating Ambient
0 to +70
Package power dissipation
1.0
Unit
V
uA
V
V
V
V
V
oC
oC
W
PACVGA200
ELECTRICAL OPERATING CHARACTERISTICS
(over operating conditions unless specified otherwise)
Symbol
ICC1
ICC2, 3
ICC4
Parameter
VCC1 supply current
VCC2, VCC3 supply current
VCC4 supply current
Conditions
VCC1 = 5V; VIDEO inputs at VCC1 or GND
VCC2 = VCC3 = 5V
VCC4 = 5V; SYNC inputs at GND or VCC4;
PWR_UP pin at VCC4; SYNC outputs unloaded
VCC4 = 5V; SYNC inputs at 3.0V; PWR_UP
pin at VCC4; SYNC outputs unloaded
VCC4 = 5V; PWR_UP input at GND; SYNC
outputs unloaded
MIN TYP MAX UNIT
10 uA
10 uA
10 uA
200 uA
10 uA
VBIAS
RT
V IH
V IL
V OH
VOL
Rb, Rp
Rc
IN
IOFF
VON
VBIAS open circuit voltage
VIDEO termination resistance
RT resistance matching
Logic High input voltage1
Logic Low input voltage1
Logic High output voltage1
Logic Low output voltage1
Resistor value
VCC 2 pull-down resistor
Input current
VIDEO inputs
HSYNC, VSYNC inputs
OFF state leakage current, level
shifting NFET
Voltage drop across level
shifting NFET when turned ON
No external current drawn from VBIAS pin
VCC4 = 5.0V
VCC4 = 5.0V
IOH = -4mA, VCC4 = 5.0V
IOL = 4mA, VCC4 = 5.0V
PWR_UP, VCC3 = 5.0V
VCC2 = 3.0V
VCC1 = 5V; VIN = VCC1 or GND
VCC4 = 5V; VIN = VCC4 or GND
(VCC2 - VDDC_IN) < 0.4V; VDDC_OUT= VCC2
(VCC2 - VDDC_OUT) < 0.4V; VDDC_IN= VCC2
VCC2 = 2.5V; VS = GND, IDS = 3mA
71.25
2.0
4.4
0.5
0.5
VCC4-0.8
75
1
1
1.5
78.75
2
0.8
0.4
2
3
V
Ω
%
V
V
V
V
MΩ
MΩ
±1
±1
10
10
0.15
µA
µA
µA
µA
V
CIN Input capacitance 3
VIDEO_1, VIDEO_2, VIDEO_3
VCC1 = 5.0V; VIN = 2.5V; measured at 1MHz
4.0
pF
VCC1 = 2.5V; VIN = 1.25V; measured at 1MHz
4.5
tPLH SYNC drivers L-H propagation delay CL = 50 pF; VCC = 5V; Input tr and tf < 5ns
8 12 ns
tPHL SYNC drivers H-L propagation delay CL = 50 pF; VCC = 5V; Input tr and tf < 5ns
8 12 ns
tr, tf SYNC drivers output rise & fall times CL = 50 pF; VCC = 5V; Input tr and tf < 5ns 7 ns
VESD ESD withstand voltage2, 3
VCC1 = VCC3 = VCC4 = 5V
±8 kV
Note 1: These parameter applies only to the HSYNC and VSYNC channels.
Note 2:
Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC3 and VCC4 must be bypassed
to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins
are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD
protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
Note 3: This parameter is guaranteed by design and characterization.
©2000 California Micro Devices Corp. All rights reserved.
2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
4/00
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CALIFORNIA MICRO DEVICES
Typical Connection Diagram
PACVGA200
A resistor may be necessary between the VCC3 pin and ground if protection against a stream of ESD pulses is required
while the PACVGA200 is in the power-down state. The value of this resistor should be chosen such that the extra
charge deposited into the VCC3 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs.
The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PACVGA200
is in the power-up state, an internal discharge resistor is connected to ground via an FET switch for this purpose.
For the same reason, VCC1 and VCC4 may also require bypass capacitor discharging resistors to ground if there are no
other components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75R resistors is not connected internally to GNDD and should ideally be connected
to the ground of the video DAC IC.
STANDARD PART ORDERING INFORMATION
Package
Ordering Part Number
Pins Style
Part Marking
24 QSOP
PACVGA200Q
When placing an order please specify desired shipping: Tubes or Tape & Reel.
© 2000 California Micro Devices Corp. All rights reserved.
4/00 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
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