PAD SERIES Linear Integrated Systems FEATURES DIRECT REPLACEMENT FOR SILICONIX PAD SERIES REVERSE BREAKDOWN VOLTAGE REVERSE CAPACITANCE ABSOLUTE MAXIMUM RATINGS1 @ 25 °C (unless otherwise stated) Maximum Temperatures Storage Temperature Operating Junction Temperature Maximum Power Dissipation Continuous Power Dissipation (PAD) Continuous Power Dissipation (J/SSTPAD) Maximum Currents Forward Current (PAD) Forward Current (J/SSTPAD) 50mA 10mA * Cathode tied to Case 300mW 350mW -65 to +150 °C -55 to +135 °C JPAD TO-92 BOTTOM VIEW A 1 3 PICO AMPERE DIODES BVR ≥ -30V Crss ≤ 2.0pF PAD1,2,5 TO-72 BOTTOM VIEW 2 PAD* TO-72 BOTTOM VIEW 2 K K* C A 1 SSTPAD SOT-23 TOP VIEW K 1 3 K 1 A 2 A K 2 COMMON ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated) SYMBOL BVR VF Crss CHARACTERISTIC Reverse Breakdown Voltage Forward Voltage Total Reverse Capacitance PAD1,5 All Others ALL PAD ALL SSTPAD ALL JPAD MIN -45 -30 -35 0.8 0.5 1.5 1.5 0.8 2 pF V IR = -1µA IF = 5mA VR = -5V, f = 1MHz TYP MAX UNITS CONDITIONS SPECIFIC ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated) SYMBOL CHARACTERISTIC (SST/J)PAD1 (SST/J)PAD2 (SST/J)PAD5 IR Maximum Reverse 2 Leakage Current (SST/J)PAD10 (SST/J)PAD20 (SST/J)PAD50 (SST/J)PAD100 (SST/J)PAD200 (SST/J)PAD500 PAD2 -1 -2 -5 -10 -20 -50 -100 -5 -10 -20 -50 -100 -200 -500 -5 -10 -20 -50 pA VR = -20V JPAD2 SSTPAD2 UNITS CONDITIONS Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Figure 1. Operational Amplifier Protection Input Differential Voltage limited to 0.8V (typ) by JPADs D1 and D2. Common Mode Input voltage limited by JPADs D3 and D4 to ±15V. Figure 2. Sample and Hold Circuit Typical Sample and Hold circuit with clipping. JPAD diodes reduce offset voltages fed capacitively from the JFET switch gate. FIGURE 1 FIGURE 2 +V JPAD20 D1 D3 D2 D4 OP-27 + -V D2 +V JPAD5 D1 2N4117A 2N4393 C ein +15V -15V CONTROL SIGNAL R VOUT TO-72 Three Lead 0.195 DIA. 0.175 0.030 MAX. 0.230 DIA. 0.209 0.150 0.115 0.170 0.195 0.175 0.195 TO-92 0.130 0.155 0.045 0.060 0.89 1.03 SOT-23 1 1.78 2.05 0.37 0.51 LS XXX YYWW 3 2 1.20 1.40 2.10 2.64 0.085 0.180 2.80 3.04 3 LEADS 0.019 DIA. 0.016 0.100 0.500 MIN. 0.016 0.022 0.500 0.610 0.014 0.020 0.89 1.12 0.050 0.013 0.100 1 2 0.55 DIMENSIONS IN MILLIMETERS 1 2 3 0.095 0.105 DIMENSIONS IN INCHES. 45° 0.046 0.036 0.048 0.028 1. 2. Absolute maximum ratings are limiting values above which serviceability may be impaired. The PAD type number denotes its maximum reverse current value in pico amperes. Devices with IR values intermediate to those shown are available upon request. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 PAD50 DIODES Datasheet pdf - AMPERE DIODES. Equivalent, Catalog

AMPERE DIODES. PAD50 Datasheet

PAD50 DIODES. Datasheet pdf. Equivalent

PAD50 Datasheet
Recommendation PAD50 Datasheet
Part PAD50
Description PICO AMPERE DIODES
Feature PAD50; PAD SERIES Linear Integrated Systems FEATURES DIRECT REPLACEMENT FOR SILICONIX PAD SERIES REVERSE BR.
Manufacture Linear Integrated Systems
Datasheet
Download PAD50 Datasheet





Linear Integrated Systems PAD50
Linear Integrated Systems
PAD SERIES
PICO AMPERE DIODES
FEATURES
DIRECT REPLACEMENT FOR SILICONIX PAD SERIES
REVERSE BREAKDOWN VOLTAGE
REVERSE CAPACITANCE
ABSOLUTE MAXIMUM RATINGS1
BVR -30V
Crss 2.0pF
@ 25 °C (unless otherwise stated)
Maximum Temperatures
Storage Temperature
-65 to +150 °C
Operating Junction Temperature
-55 to +135 °C
Maximum Power Dissipation
Continuous Power Dissipation (PAD)
300mW
Continuous Power Dissipation (J/SSTPAD)
350mW
Maximum Currents
Forward Current (PAD)
50mA
Forward Current (J/SSTPAD)
10mA
PAD1,2,5
TO-72
BOTTOM VIEW
2K
A 1 3C
JPAD
TO-92
BOTTOM VIEW
KA
12
PAD*
TO-72
BOTTOM VIEW
2 K*
A1
SSTPAD
SOT-23
TOP VIEW
K1
K2
3A
* Cathode tied to Case
COMMON ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)
SYMBOL CHARACTERISTIC
MIN TYP MAX
BVR
Reverse Breakdown
Voltage
ALL PAD
ALL SSTPAD
ALL JPAD
-45
-30
-35
VF Forward Voltage
Crss Total Reverse Capacitance
PAD1,5
All Others
0.8 1.5
0.5 0.8
1.5 2
UNITS
V
pF
CONDITIONS
IR = -1µA
IF = 5mA
VR = -5V, f = 1MHz
SPECIFIC ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)
SYMBOL CHARACTERISTIC
PAD2
JPAD2
SSTPAD2
(SST/J)PAD1
-1
(SST/J)PAD2
-2
(SST/J)PAD5
-5
-5
-5
(SST/J)PAD10
-10
-10
-10
IR
Maximum Reverse
Leakage Current2
(SST/J)PAD20
-20
-20
-20
(SST/J)PAD50
-50
-50
-50
(SST/J)PAD100
-100
-100
(SST/J)PAD200
-200
(SST/J)PAD500
-500
UNITS
pA
CONDITIONS
VR = -20V
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261



Linear Integrated Systems PAD50
Figure 1. Operational Amplifier Protection
Input Differential Voltage limited to 0.8V (typ) by JPADs D1 and D2. Common
Mode Input voltage limited by JPADs D3 and D4 to ±15V.
Figure 2. Sample and Hold Circuit
Typical Sample and Hold circuit with clipping. JPAD diodes reduce offset
voltages fed capacitively from the JFET switch gate.
FIGURE 1
FIGURE 2
JPAD20
-
D1 D2 OP-27
+
D3 D4
+15V -15V
ein CONTROL
SIGNAL
+V -V
JPAD5
D1
D2
2N4393
C
+V
2N4117A
R VOUT
TO-72
Three Lead
0.195 DIA.
0.175
0.030
MAX.
0.230 DIA.
0.209
0.150
0.115
TO-92
SOT-23
0.175
0.195
0.170 LS XXX
0.195 YYWW
0.130
0.155
0.045
0.060
0.89
1.03
1.78
2.05
1
2
0.37
0.51
3 2.80
3.04
3 LEADS
0.019 DIA.
0.016
0.100
0.500 MIN.
0.050
45°
0.046
0.036
12
3
0.048
0.028
0.500
0.610
0.016
0.022
0.014
0.020
12
0.095
0.105
DIMENSIONS
IN INCHES.
0.89
1.12
1.20
1.40
2.10
2.64
0.085
0.180
0.013
0.100
0.55
DIMENSIONS IN
MILLIMETERS
1. Absolute maximum ratings are limiting values above which serviceability may be impaired.
2. The PAD type number denotes its maximum reverse current value in pico amperes. Devices with IR values intermediate to those shown
are available upon request.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261





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