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PAL DEVICE. PALC22V10D Datasheet |
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For new designs, please refer to the PALCE22V10.
PALC22V10D
Features
D Advanced secondĆgeneration PAL arĆ
chitecture
D Low power
Ċ 90 mA max. commercial (10 ns)
Ċ 130 mA max. commercial (7.5 ns)
D CMOS Flash EPROM technology for
electrical erasability and reprogramĆ
mability
D Variable product terms
Ċ 2 xĂ(8 through ā16) product terms
D UserĆprogrammable macrocell
Ċ Output polarity control
Ċ Individually selectable for regisĆ
tered or combinatorial operation
D Up to 22 input terms and 10 outputs
Flash Erasable,
Reprogrammable CMOS PALR Device
D DIP, LCC, and PLCC available
Ċ 7.5 ns commercial version
5 ns tCO
5 ns tS
7.5 ns tPD
133ĆMHz state machine
Ċ 10 ns military and industrial verĆ
sions
6 ns tCO
6 ns tS
10 ns tPD
110ĆMHz state machine
Ċ 15Ćns commercial and military
versions
Ċ 25Ćns commercial and military
versions
D High reliability
Ċ Proven Flash EPROM technology
Ċ 100% programming and functional
testing
Functional Description
The Cypress PALC22V10D is a CMOS
Flash Erasable secondĆgeneration proĆ
grammable array logic device. It is imĆ
plemented with the familiar sumĆofĆproĆ
ducts (ANDĆOR) logic structure and the
programmable macrocell.
The PALC22V10D is executed in a 24Ćpin
300Ćmil molded DIP, a 300Ćmil cerDIP, a
28Ćlead square ceramic leadless chip carriĆ
er, a 28Ćlead square plastic leaded chip carĆ
rier, and provides up to 22 inputs and 10
outputs. The 22V10D can be electrically
Logic Block Diagram (PDIP/CDIP)
VSS
I
II
I
12 11
10
98
I
7
II
65
II
43
I CP/I
21
8 10
12 14
PROGRAMMABLE
AND ARRAY
(132 X 44)
16 16
14
12 10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13 14 15
I
I/O9
I/O8
Pin Configuration
16
I/O 7
17
I/O6
LCC
Top View
18
I/O5
19
I/O4
20
I/O3
21
I/O2
22
I/O1
PLCC
Top View
23
I/O0
24
VCC
V10DĆ1
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
V10DĆ2
PAL is a registered trademark of Advanced Micro Devices.
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
V10DĆ3
DCypress Semiconductor Corporation
3901 North First Street
1
D DSan Jose
DCA 95134
408-943-2600
July 1991 - Revised October 1995
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PALC22V10D
Functional Description (continued)
erased and reprogrammed. The programmable macrocell provides
the capability of defining the architecture of each output individuĆ
ally. Each of the 10 potential outputs may be specified as regisĆ
tered" or combinatorial." Polarity of each output may also be inĆ
dividually selected, allowing complete flexibility of output
configuration. Further configurability is provided through array"
configurable output enable" for each potential output. This feaĆ
ture allows the 10 outputs to be reconfigured as inputs on an indiĆ
vidual basis, or alternately used as a combination I/O controlled by
the programmable array.
PALC22V10D features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms per
output. By providing this variable structure, the PAL C 22V10D is
optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PALC22V10D include a synĆ
chronous preset and an asynchronous reset product term. These
product terms are common to all macrocells, eliminating the need
to dedicate standard product terms for initialization functions. The
device automatically resets upon powerĆup.
The PALC22V10D, featuring programmable macrocells and variĆ
able product terms, provides a device with the flexibility to impleĆ
ment logic functions in the 500Ć to 800ĆgateĆarray complexity.
Since each of the 10 output pins may be individually configured as
inputs on a temporary or permanent basis, functions requiring up
to 21 inputs and only a single output and down to 12 inputs and 10
outputs are possible. The 10 potential outputs are enabled using
product terms. Any output pin may be permanently selected as an
output or arbitrarily enabled as an output and an input through the
selective use of individual product terms associated with each outĆ
put. Each of these outputs is achieved through an individual proĆ
grammable macrocell.ThesemacrocellsareprogrammabletoproĆ
vide a combinatorial or registered inverting or nonĆinverting
output. In a registered mode of operation, the output of the regisĆ
ter is fed back into the array, providing current status information
to the array. This information is available for establishing the next
result in applications such as control state machines. In a combinaĆ
torial configuration, the combinatorial output or, if the output is
disabled, the signal present on the I/O pin is made available to the
array. The flexibility provided by both programmable product term
control of the outputs and variable product terms allows a signifiĆ
cant gain in functional density through the use of programmable
logic.
Along with this increase in functional density, the Cypress
PALC22V10D provides lowerĆpower operation through the use of
CMOS technology, and increased testability with Flash reproĆ
grammability.
Configuration Table
Registered/Combinatorial
C1
C0
00
01
10
11
Configuration
Registered/Active LOW
Registered/Active HIGH
Combinatorial/Active LOW
Combinatorial/Active HIGH
Macrocell
AR
DQ
OUTPUT
SELECT
MUX
CP
Q
S1 S0
SP
INPUT/
FEEDBACK
MUX
S1
C1
C0
MACROCELL
V10DĆ4
2
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PALC22V10D
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . -65_C to +150_C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Output Current into Outputs (LOW) . . . . . . . . . . . . . . 16 mA
DC Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 12.5V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) . . . . . . . . . . . . . . >2001V
Operating Range
Range
Commercial
Military[1]
Industrial
Ambient
Temperature
0_C to +75_C
-55_C to +125_C
-40_C to +85_C
VCC
5V ±5%
5V ±10%
5V ±10%
LatchĆUp Current . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
VOH
VOL
VIH
VIL[4]
IIX
IOZ
ISC
ICC1
ICC2[6]
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
VCC = Min.,
VIN = VIH or VIL
IOH = -3.2 mA
IOH = -2 mA
Com'l
Mil/Ind
VCC = Min.,
VIN = VIH or VIL
IOL = 16 mA
IOL = 12 mA
Com'l
Mil/Ind
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Guaranteed Input Logical LOW Voltage for All Inputs[3]
Input Leakage Current
VSS < VIN < VCC, VCC = Max.
Output Leakage Current
VCC = Max., VSS < VOUT < VCC
Output Short Circuit Current VCC = Max., VOUT = 0.5V[5,Ă6]
Standby Power Supply
Current
VCC = Max.,
10, 15, 25 ns
VIN = GND,
Outputs Open
in
7.5 ns
Unprogrammed
Device
15, 25 ns
10 ns
Com'l
Mil/Ind
Operating Power Supply
Current
VCC = Max., VIL =
0V, VIH = 3V,
Output Open, DeĆ
vice Programmed as
a 10ĆBit Counter,
f = 25 MHz
10, 15, 25 ns
7.5 ns
15, 25 ns
10 ns
Com'l
Mil/Ind
Min.
2.4
2.0
-0.5
-10
-40
-30
Max. Unit
V
0.5 V
V
0.8 V
10 mA
40 mA
-90 mA
90 mA
130 mA
120 mA
120 mA
110 mA
140 mA
130 mA
130 mA
Capacitance[6]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
Min.
Max.
10
10
Unit
pF
pF
Endurance Characteristics[6]
Parameter
N
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Min.
100
Max.
Unit
Cycles
Notes:
1. TA is the instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing inĆ
formation.
3. These are absolute values with respect to device ground. All overĆ
shoots due to system or tester noise are included.
4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.
5. Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = 0.5V has been choĆ
sen to avoid test problems caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect
these parameters.
3
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