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QL2009-XPB256I Datasheet, Equivalent, and Flexibility.3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| Part | QL2009-XPB256I |
|---|---|
| Description | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| Feature | 3. 3V and 5. 0V pASIC 2 FPGA Combining Spe ed, Density, Low Cost and Flexibility R ev. C pASIC 2 HIGHLIGHTS ® QL2009 U ltimate Verilog/VHDL Silicon Solution - Abundant, high-speed interconnect elimi nates manual routing -Flexible logic ce ll provides high efficiency and perform ance -Design tools produce fast, effici ent Verilog/VHDL synthesis Speed, Dens ity, Low Cost and Flexibility in One De vice 9,000 usable ASIC gates, 225 I/O pins -16-bit counter speeds exceeding 2 00 MHz -9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os -3-layer me tal ViaLink® process for small die siz es -100% routabl . |
| Manufacture | ETC |
| Datasheet |
| Part | QL2009-XPB256I |
|---|---|
| Description | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility |
| Feature | 3. 3V and 5. 0V pASIC 2 FPGA Combining Spe ed, Density, Low Cost and Flexibility R ev. C pASIC 2 HIGHLIGHTS ® QL2009 U ltimate Verilog/VHDL Silicon Solution - Abundant, high-speed interconnect elimi nates manual routing -Flexible logic ce ll provides high efficiency and perform ance -Design tools produce fast, effici ent Verilog/VHDL synthesis Speed, Dens ity, Low Cost and Flexibility in One De vice 9,000 usable ASIC gates, 225 I/O pins -16-bit counter speeds exceeding 2 00 MHz -9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os -3-layer me tal ViaLink® process for small die siz es -100% routabl . |
| Manufacture | ETC |
| Datasheet |
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