W210 Datasheet PDF Download, Cypress Semiconductor





(PDF) W210 Datasheet Download

Part Number W210
Description Spread Spectrum FTG for VIA K7 Chipset
Manufacture Cypress Semiconductor
Total Page 14 Pages
PDF Download Download W210 Datasheet PDF

Features: W210 Spread Spectrum FTG for VIA K7 Chi pset Features • Maximized EMI Suppres sion using Cypress’s Spread Spectrum technology • Single-chip system frequ ency synthesizer for VIA K7 chipset • One pair of differential CPU outputs f or K7 Processor • One open-drain CPU output for VIA K7 chipset • Six copie s of PCI output • One 48-MHz output f or USB • One 24-MHz or 48-MHz output for SIO • Two buffered reference outp uts • Thirteen SDRAM outputs provide support for 3 DIMMs • Supports freque ncies up to 200 MHz • I2C™ interfac e for programming • Power management control inputs • Available in 48-pin SSOP Table 1. Mode Input Table Mode 0 1 Pin 2 CPU_STOP# REF0 Key Specificatio ns CPU to CPU Output Skew: ............ ............................. 175 ps PC I to PCI Output Skew: ................. ........................... 500 ps VDDQ 3: .................................... ................................ 3.3V± 5% Table 2. Pin Selectable Frequency Input Address CPU FS3 FS2 FS1 FS0 (MHz) 1 1 1 1 133.3 1 .

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W210
Spread Spectrum FTG for VIA K7 Chipset
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Single-chip system frequency synthesizer for VIA K7
chipset
• One pair of differential CPU outputs for K7 Processor
• One open-drain CPU output for VIA K7 chipset
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 200 MHz
• I2C™ interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
VDDQ3
REF0/(CPU_STOP#)
REF1/FS0
PWRDWN#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
I2C
Logic
PLL2
÷2
SDRAMIN
I2C is a trademark of Philips Corporation.
CPUT_CS
CPUT0
CPUC0
VDDQ3
PCI0/MODE
PCI1/FS1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS2
24_48MHz/FS3
VDDQ3
SDRAM0:12
13
Table 1. Mode Input Table
Mode
0
1
Pin 2
CPU_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
CPU
(MHz)
1111
133.3
1110
75
1101
100.2
1100
66.8
1011
79
1010
110
1001
115
1000
120
0111
133.3
0110
83.3
0101
100.2
0100
66.8
0011
124
0010
129
0001
138
0000
143
PCI0:5
(MHz)
33.3
37.5
33.3
33.4
39.5
36.7
38.3
30
33.3
27.7
33.3
33.4
31.0
32.3
34.5
35.8
Spread
Spectrum
±0.5%
±0.5%
±0.5%
±0.5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Pin Configuration[1]
VDDQ3
REF0/(CPU_STOP#)
GND
X1
X2
VDDQ3
PCI0/MODE
PCI1/FS1*
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS0*
47 GND
46 CPUT_CS
45 GND
44 CPUC0
43 CPUT0
42 VDDQ3
41 PWRDWN#*
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS2*
25 24_48MHz/FS3^
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 11, 2000, rev. *C

                    
                    






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