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74LS73 Datasheet, Equivalent, EDGE-TRIGGERED FLIP-FLOP.

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

 

 

 

Part 74LS73
Description DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Feature SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGG ERED FLIP-FLOP The SN54LS / 74LS73A off ers individual J, K, clear, and clock i nputs.
These dual flip-flops are design ed so that when the clock goes HIGH, th e inputs are enabled and data will be a ccepted.
The logic level of the J and K inputs may be allowed to change when t he clock pulse is HIGH and the bistable will perform according to the truth ta ble as long as minimum set-up times are observed.
Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHO TTKY LOGIC DI .
Manufacture Motorola
Datasheet
Download 74LS73 Datasheet
Part 74LS73
Description DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Feature SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGG ERED FLIP-FLOP The SN54LS / 74LS73A off ers individual J, K, clear, and clock i nputs.
These dual flip-flops are design ed so that when the clock goes HIGH, th e inputs are enabled and data will be a ccepted.
The logic level of the J and K inputs may be allowed to change when t he clock pulse is HIGH and the bistable will perform according to the truth ta ble as long as minimum set-up times are observed.
Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHO TTKY LOGIC DI .
Manufacture Motorola
Datasheet
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