74LS73 FLIP-FLOP Datasheet

74LS73 Datasheet, PDF, Equivalent


Part Number

74LS73

Description

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Manufacture

Motorola

Total Page 3 Pages
Datasheet
Download 74LS73 Datasheet


74LS73
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH and the bistable will per-
form according to the truth table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on the negative-going edge of
the clock pulse.
SN54/74LS73A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
Q
13 (8)
K
3 (10)
LOGIC DIAGRAM (Each Flip-Flop)
1 (15)
CLOCK (CP)
Q
12 (9)
CLEAR
2 (6)
J
14 (7)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
CD J
K
OUTPUTS
QQ
Reset (Clear)
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
LXXLH
Hh h q q
H l hLH
Hh l HL
Hl l qq
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) = prior to the HIGH to LOW clock transition.
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
14 J
Q 12 7 J
Q9
1 CP
5 CP
3 K CD Q 13 10 K CD Q 8
2
VCC = PIN 4
GND = PIN 11
6
FAST AND LS TTL DATA
5-68

74LS73
SN54 / 74LS73A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
TA Operating Ambient Temperature Range
54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High
IOL Output Current — Low
54, 74
54
74
– 0.4
4.0
8.0
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
VIH Input HIGH Voltage
Min Typ Max Unit
Test Conditions
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54 0.7 Guaranteed Input LOW Voltage for
74 0.8 V All Inputs
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5
74 2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
IIH Input HIGH Current
54, 74
74
J, K
Clear
Clock
J, K
Clear
Clock
0.25 0.4
0.35 0.5
20
60
80
0.1
0.3
0.4
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
J, K
Clear, Clock
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1)
– 20
ICC Power Supply Current
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
–100
6.0
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay,
Clock to Output
30 45
15 20
15 20
mA
mA
Unit
MHz
ns
ns
VCC = MAX
VCC = MAX
Test Conditions
Figure 1
Figure 1
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear Pulse Width
Setup Time
Hold Time
Limits
Min Typ Max
20
25
20
0
Unit
ns
ns
ns
ns
Test Conditions
Figure 1
Figure 2
Figure 1
VCC = 5.0 V
FAST AND LS TTL DATA
5-69


Features SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGG ERED FLIP-FLOP The SN54LS / 74LS73A off ers individual J, K, clear, and clock i nputs. These dual flip-flops are design ed so that when the clock goes HIGH, th e inputs are enabled and data will be a ccepted. The logic level of the J and K inputs may be allowed to change when t he clock pulse is HIGH and the bistable will perform according to the truth ta ble as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHO TTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 13 (8 ) Q 12 (9) 1 CLEAR 2 (6) K 3 (10) 1 (15) CLOCK (CP) J 14 (7) 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SO IC CASE 751A-02 ORDERING INFORMATION S N54LSXXJ SN74LSXXN SN74LSXXD OUTPUTS K X h h l l Q L q L H q Q H q H L q Ceram ic Plastic SOIC MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE CD Reset (Clear) Toggle Load “0” (Res.
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