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74LVT20 Data Sheet

3.3V Dual 4-input NAND gate

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74LVT20

INTEGRATED CIRCUITS 74LVT20 3.3V Dual 4-input NAND gate Product specification IC24 Data Handbook 1996 Aug 28 Philips Semiconductors Philips Semiconductors Product specification 3.3V Dual 4-input NAND gate 74LVT20 QUICK REFERENCE DATA SYMBOL PARAMETER Propagation delay An, Bn, Cn, Dn to Yn Inp.

74LVT20

Download 74LVT20 Datasheet

INTEGRATED CIRCUITS 74LVT20 3.3V Dual 4-input NAND gate Product specification IC24 Data Handbook 1996 Aug 28 Philips Semiconductors Philips Semiconductors Product specification 3.3V Dual 4-input NAND gate 74LVT20 QUICK REFERENCE DATA SYMBOL PARAMETER Propagation delay An, Bn, Cn, Dn to Yn Input capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 3.3V TYPICAL UNIT LOGIC DIAGRAM A0 B0 C0 1 2 6 4 5 Y0 tPLH tPHL 3.4 3.2 ns D0 CIN ICCL VI = 0V or 3.0V Outputs Low; VCC = 3.6V 3 0.5 pF mA VCC = Pin 14 GND = Pin 7 A1 B1 C1 D1 9 10 8 12 13 Y1 PIN CONFIGURATION A0 B0 NC C0 D0 Y0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SA00352 LOGIC SYMBOL (IEEE/IEC) VCC D1 1 C1 2 NC 4 B1 5 A1 Y1 6 & SA00350 9 10 8 12 PIN DESCRIPTION PIN NUMBER 1, 2, 4, 5, 9, 10, 12, 13 6, 8 7 14 SYMBOL An, Bn, Cn, Dn Yn GND VCC N.




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