NAND gate. 74LVT20 Datasheet

74LVT20 gate. Datasheet pdf. Equivalent

Part 74LVT20
Description 3.3V Dual 4-input NAND gate
Feature INTEGRATED CIRCUITS 74LVT20 3.3V Dual 4-input NAND gate Product specification IC24 Data Handbook 19.
Manufacture NXP
Datasheet
Download 74LVT20 Datasheet




74LVT20
INTEGRATED CIRCUITS
74LVT20
3.3V Dual 4-input NAND gate
Product specification
IC24 Data Handbook
1996 Aug 28
Philips
Semiconductors



74LVT20
Philips Semiconductors
3.3V Dual 4-input NAND gate
Product specification
74LVT20
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
Tamb = 25°C;
GND = 0V
Propagation
tPLH delay
CL = 50pF;
tPHL An, Bn, Cn, Dn VCC = 3.3V
to Yn
CIN
Input
capacitance
VI = 0V or 3.0V
ICCL
Total supply
current
Outputs Low;
VCC = 3.6V
TYPICAL UNIT
3.4
3.2
ns
3 pF
0.5 mA
PIN CONFIGURATION
A0 1
B0 2
NC 3
C0 4
D0 5
Y0 6
GND 7
14 VCC
13 D1
12 C1
11 NC
10 B1
9 A1
8 Y1
SA00350
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
NAME AND FUNCTION
1, 2, 4, 5, 9,
10, 12, 13
An, Bn,
Cn, Dn
Data inputs
6, 8 Yn Data outputs
7 GND Ground (0V)
14 VCC Positive supply voltage
LOGIC SYMBOL
1 2 4 5 9 10 12 13
A0 B0 C0 D0 A1 B1 C1 D1
VCC = Pin 14
GND = Pin 7
Y0 Y1
68
SA00351
LOGIC DIAGRAM
A0
B0
C0
D0
1
2
4
5
VCC = Pin 14
GND = Pin 7
9
A1
10
B1
12
C1
13
D1
6
Y0
8
Y1
LOGIC SYMBOL (IEEE/IEC)
1&
2
4
5
6
SA00352
9
10
12
13
FUNCTION TABLE
INPUTS
Dna Dnb Dnc
LXX
XLX
XXL
XXX
HH
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
H
8
SF00068
OUTPUT
Dnd Qn
XH
XH
XH
LH
HL
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP
14-Pin Plastic TSSOP
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT20 D
74LVT20 DB
74LVT20 PW
NORTH AMERICA
74LVT20 D
74LVT20 DB
74LVT20PW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
1996 Aug 28
2 853-1871 17244







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