CONTROLLER IOAPIC. 82093AA Datasheet

82093AA Datasheet PDF, Equivalent


Part Number

82093AA

Description

I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

Manufacture

Intel Corporation

Total Page 20 Pages
PDF Download
Download 82093AA Datasheet


82093AA Datasheet
E
PRELIMINARY
82093AA I/O ADVANCED
PROGRAMMABLE INTERRUPT
CONTROLLER (IOAPIC)
Provides Multiprocessor Interrupt
Management
Dynamic Interrupt Distribution-
Routing Interrupt to the Lowest
Priority Processor
Software Programmable Control of
Interrupt Inputs
Off Loads Interrupt Related Traffic
From the Memory Bus
24 Programmable Interrupts
13 ISA Interrupts Supported
4 PCI Interrupts
1 Interrupt/SMI# Rerouting
2 Motherboard Interrupts
1 Interrupt Used for INTR Input
3 General Purpose Interrupts
Independently Programmable for
Edge/Level Sensitivity Interrupts
Each Interrupt Can Be Programmed
to Respond to Active High or Low
Inputs
X-Bus Interface
CS For Flexible Decode of the
IOAPIC Device.
Index Register Interface for
Optimum Memory Usage
Registers are 32-Bit Wide to Match
the PCI to Host Bridge Architecture
Package 64-Pin PQFP
The 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) provides multi-processor interrupt
management and incorporates both static and dynamic symmetric interrupt distribution across all processors. In
systems with multiple I/O subsystems, each subsystem can have its own set of interrupts. Each interrupt pin is
individually programmable as either edge or level triggered. The interrupt vector and interrupt steering
information can be specified per interrupt. An indirect register accessing scheme optimizes the memory space
needed to access the IOAPIC’s internal registers. To increase system flexibility when assigning memory space
usage, the The IOAPIC’s 2-register memory space is re-locatable.
D[7:0]
D/I#
A[1:0]
RD#
WR#
CS#
APCIREQ#
APICACK1#
A P I CA C K 2#
RESET
CLK
System
Bus
Interface
Clock
And
Reset
APIC
Bus
Interface
Interrupt
Controller
Test
APCID[1:0]
APCICLK
APCID[1:0]
APCICLK
APCICLK
TESTIN#
IOA_BLK
Figure 1. IOAPIC Simplified Block Diagram
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in
medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The
82093AA IOAPIC may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are
the property of their respective owners.
© INTEL CORPORATION 1996
May 1996
Order Number: 290566-001

82093AA Datasheet
82093AA (IOAPIC)
E
CONTENTS
PAGE
1.0. OVERVIEW ......................................................................................................................................................3
2.0. SIGNAL DESCRIPTION ..................................................................................................................................5
2.1. System Bus Signals......................................................................................................................................5
2.2. Clock and Reset Signals...............................................................................................................................6
2.3. APIC Bus Interface .......................................................................................................................................6
2.4. Interrupt Signals ............................................................................................................................................6
2.5. Test and Power Signals ................................................................................................................................7
3.0. REGISTER DESCRIPTION .............................................................................................................................8
3.1. Memory Mapped Registers for Accessing IOAPIC Registers......................................................................9
3.1.1. IOREGSEL—I/O REGISTER SELECT REGISTER .............................................................................9
3.1.2. IOWIN—I/O WINDOW REGISTER.......................................................................................................9
3.2. IOAPIC Registers .........................................................................................................................................9
3.2.1. IOAPICID—IOAPIC IDENTIFICATION REGISTER .............................................................................9
3.2.2. IOAPICVER—IOAPIC VERSION REGISTER....................................................................................10
3.2.3. IOAPICARB—IOAPIC ARBITRATION REGISTER............................................................................10
3.2.4. IOREDTBL[23:0]—I/O REDIRECTION TABLE REGISTERS ............................................................11
4.0. FUNCTIONAL DESCRIPTION ......................................................................................................................14
4.1. INTIN23/SMI# and SMIOUT# Functionality................................................................................................14
5.0. PINOUT AND PACKAGE SPECIFICATIONS ..............................................................................................15
5.1. Pinout Specifications...................................................................................................................................15
5.2. Package Specifications...............................................................................................................................17
6.0. TESTABILITY.................................................................................................................................................18
6.1. Tri-State Of All Output Pins.........................................................................................................................18
6.2. Drive 1’s to all the output pins.....................................................................................................................18
6.3. Drive 0’s to all the output pins.....................................................................................................................19
6.4. NAND Tree .................................................................................................................................................19
2 PRELIMINARY


Features Datasheet pdf E PRELIMINARY 82093AA I/O ADVANCED PRO GRAMMABLE INTERRUPT CONTROLLER (IOAPIC)  3 General Purpose Interrupts  I ndependently Programmable for Provides Multiprocessor Interrupt Management Dynamic Interrupt DistributionRouting Interrupt to the Lowest Priority Proce ssor  Software Programmable Control of Interrupt Inputs  Off Loads Inter rupt Related Traffic From the Memory Bu s 24 Programmable Interrupts  13 ISA Interrupts Supported  4 PCI Interru pts  1 Interrupt/SMI# Rerouting  2 Motherboard Interrupts  1 Interrup t Used for INTR Input Edge/Level Sensi tivity Interrupts  Each Interrupt Ca n Be Programmed to Respond to Active H igh or Low Inputs X-Bus Interface  C S For Flexible Decode of the IOAPIC Dev ice.  Index Register Interface for O ptimum Memory Usage  Registers are 3 2-Bit Wide to Match the PCI to Host Bri dge Architecture Package 64-Pin PQFP T he 82093AA I/O Advanced Programmable In terrupt Controller (IOAPIC) provides multi-processor interrupt management and incorporates .
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