DMA Controller. 82C37A Datasheet

82C37A Datasheet PDF, Equivalent


Part Number

82C37A

Description

CMOS High Performance Programmable DMA Controller

Manufacture

Intersil Corporation

Total Page 23 Pages
PDF Download
Download 82C37A Datasheet


82C37A Datasheet
82C37A
March 1997
CMOS High Performance
Programmable DMA Controller
Features
Description
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
Ordering Information
5MHz
CP82C37A-5
IP82C37A-5
CS82C37A-5
IS82C37A-5
CD82C37A-5
ID82C37A-5
MD82C37A-5/B
5962-9054301MQA
MR82C37A-5/B
5962-9054301MXA
PART NUMBER
8MHz
CP82C37A
IP82C37A
CS82C37A
IS82C37A
CD82C37A
ID82C37A
MD82C37A/B
5962-9054302MQA
MR82C37A/B
5962-9054302MXA
12.5MHz
CP82C37A-12
IP82C37A-12
CS82C37A-12
IS82C37A-12
CD82C37A-12
ID82C37A-12
MD82C37A-12/B
5962-9054303MQA
MR82C37A-12/B
5962-9054303MXA
PACKAGE
40 Ld PDIP
44 Ld PLCC
40 Ld CERDIP
SMD#
44 Pad CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-192
File Number 2967.1

82C37A Datasheet
Pinouts
82C37A (PDIP/CERDIP)
TOP VIEW
IOR 1
IOW 2
MEMR 3
MEMW 4
NC 5
READY 6
HLDA 7
ADSTB 8
AEN 9
HRQ 10
CS 11
CLK 12
RESET 13
DACK2 14
DACK3 15
DREQ3 16
DREQ2 17
DREQ1 18
DREQ0 19
(GND) VSS 20
40 A7
39 A6
38 A5
37 A4
36 EOP
35 A3
34 A2
33 A1
32 A0
31 VCC
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25 DACK0
24 DACK1
23 DB5
22 DB6
21 DB7
82C37A
82C37A (CLCC/PLCC)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
NC 7
39 A3
NC 8
38 A2
HLDA 9
37 A1
ADSTB 10
36 A0
AEN 11
35 VCC
HRQ 12
34 DB0
CS 13
33 DB1
CLK 14
32 DB2
RESET 15
31 DB3
DACK2 16
NC 17
30 DB4
29 NC
18 19 20 21 22 23 24 25 26 27 28
Block Diagram
EOP
RESET
CS
READY
CLK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DREQ0 -
DREQ3
HLDA
HRQ
DACK0 -
DACK3
4
4
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DECREMENTOR
TEMP WORD
COUNT REG (16)
INC/DECREMENTOR
TEMP ADDRESS
REG (16)
16-BIT BUS
16-BIT BUS
READ BUFFER
READ WRITE BUFFER
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
CURRENT
ADDRESS
(16)
CURRENT
WORD
COUNT
(16)
WRITE
BUFFER
READ
BUFFER
IO
BUFFER
A0 - A3
OUTPUT
BUFFER
A4 - A7
COMMAND
CONTROL
D0 - D1
COMMAND
(8)
MASK
(4)
REQUEST
(4)
INTERNAL DATA BUS
IO
BUFFER
MODE
(4 x 6)
STATUS
(8)
TEMPORARY
(8)
4-193


Features Datasheet pdf 82C37A March 1997 CMOS High Performance Programmable DMA Controller Descriptio n The 82C37A is an enhanced version of the industry standard 8237A Direct Memo ry Access (DMA) controller, fabricated using Intersil’s advanced 2 micron CM OS process. Pin compatible with NMOS de signs, the 82C37A offers increased func tionality, improved performance, and dr amatically reduced power consumption. T he fully static design permits gated cl ock operation for even further reductio n of power. The 82C37A controller can i mprove system performance by allowing e xternal devices to transfer data direct ly to or from system memory. Memory-to- memory transfer capability is also prov ided, along with a memory block initial ization feature. DMA requests may be ge nerated by either hardware or software, and each channel is independently prog rammable with a variety of features for flexible operation. The 82C37A is des igned to be used with an external addre ss latch, such as the 82C82, to demultiplex the most significant 8-b.
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