MM74HC132 Schmitt Trigger Datasheet

MM74HC132 Datasheet, PDF, Equivalent


Part Number

MM74HC132

Description

Quad 2-Input NAND Schmitt Trigger

Manufacture

Fairchild

Total Page 6 Pages
Datasheet
Download MM74HC132 Datasheet


MM74HC132
September 1983
Revised February 1999
MM74HC132
Quad 2-Input NAND Schmitt Trigger
General Description
The MM74HC132 utilizes advanced silicon-gate CMOS
technology to achieve the low power dissipation and high
noise immunity of standard CMOS, as well as the capability
to drive 10 LS-TTL loads.
The 74HC logic family is functionally and pinout compatible
with the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to VCC and ground.
Features
s Typical propagation delay: 12 ns
s Wide power supply range: 2V–6V
s Low quiescent current: 20 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
s Typical hysteresis voltage: 0.9V at VCC=4.5V
Ordering Code:
Order Number Package Number
Package Description
MM74HC132M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
MM74HC132SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC132MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC132N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)
Connection Diagram
Logic Diagram
Pin Assignment for DIP, SOIC, SOP, and TSSOP
Top View
© 1999 Fairchild Semiconductor Corporation DS005309.prf
www.fairchildsemi.com

MM74HC132
Absolute Maximum Ratings(Note 1)
(Note 2)
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
0.5 to +7.0V
1.5 to VCC +1.5V
0.5 to VCC +0.5V
±20 mA
±25 mA
±50 mA
65°C to +150°C
600 mW
500 mW
Recommended Operating
Conditions
Min Max Units
Supply Voltage (VCC)
26
V
DC Input or Output Voltage
0 VCC
V
(VIN, VOUT)
Operating Temperature Range (TA) 40 +125 °C
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC TA = 25°C
Typ
TA = -40 to 85°C TA = -40 to 125°C Units
Guaranteed Limits
VT+ Positive Going
Threshold Voltage
Min 2.0V
4.5V
1.0 1.0
2.0 2.0
1.0 V
2.0 V
6.0V
3.0 3.0
3.0 V
Max 2.0V
1.5 1.5
1.5 V
4.5V
3.15
3.15
3.15 V
6.0V
4.2 4.2
4.2 V
VTNegative Going
Threshold Voltage
Min 2.0V
4.5V
0.3 0.3
0.9 0.9
0.3 V
0.9 V
6.0V
1.2 1.2
1.2 V
Max 2.0V
1.0 1.0
1.0 V
4.5V
2.2 2.2
2.2 V
6.0V
3.0 3.0
3.0 V
VH Hysteresis Voltage
Min 2.0V
4.5V
0.2 0.2
0.4 0.4
0.2 V
0.4 V
6.0V
0.5 0.5
0.5 V
Max 2.0V
1.0 1.0
1.0 V
4.5V
1.4 1.4
1.4 V
6.0V
1.5 1.5
1.5 V
VOH Minimum HIGH Level
VIN = VIH or VIL
2.0V 2.0
1.9
1.9
1.9 V
Output Voltage
|IOUT| 20 µA
4.5V 4.5
4.4
4.4
4.4 V
VIN = VIH or VIL
6.0V 6.0
5.9
5.9
5.9 V
|IOUT| 4.0 mA
4.5V 4.2
3.98
3.84
3.7 V
|IOUT| 5.2 mA
6.0V 5.7
5.48
5.34
5.2 V
VOL Maximum LOW Level
VIN = VIH or VIL
2.0V
0
0.1
0.1
0.1 V
Output Voltage
|IOUT| 20 µA
4.5V
0
0.1
0.1
0.1 V
VIN = VIH or VIL
6.0V
0
0.1
0.1
0.1 V
|IOUT| 4.0 mA
4.5V 0.2
0.26
0.33
0.4 V
|IOUT| 5.2 mA
6.0V 0.2
0.26
0.33
0.4 V
IIN Maximum Input Current
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
ICC Maximum Quiescent
VIN = VCC or GND
6.0V
2.0 20
40 µA
Supply Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
www.fairchildsemi.com
2


Features MM74HC132 Quad 2-Input NAND Schmitt Trig ger September 1983 Revised February 19 99 MM74HC132 Quad 2-Input NAND Schmitt Trigger General Description The MM74HC 132 utilizes advanced silicon-gate CMOS technology to achieve the low power di ssipation and high noise immunity of st andard CMOS, as well as the capability to drive 10 LS-TTL loads. The 74HC logi c family is functionally and pinout com patible with the standard 74LS logic fa mily. All inputs are protected from dam age due to static discharge by internal diode clamps to VCC and ground. Featu res s Typical propagation delay: 12 ns s Wide power supply range: 2V–6V s Lo w quiescent current: 20 µA maximum (74 HC Series) s Low input current: 1 µA m aximum s Fanout of 10 LS-TTL loads s Ty pical hysteresis voltage: 0.9V at VCC=4 .5V Ordering Code: Order Number MM74HC 132M MM74HC132SJ MM74HC132MTC MM74HC132 N Package Number M14A M14D MTC14 N14A P ackage Description 14-Lead Small Outlin e Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 14-Le.
Keywords MM74HC132, datasheet, pdf, Fairchild, Quad, 2-Input, NAND, Schmitt, Trigger, M74HC132, 74HC132, 4HC132, MM74HC13, MM74HC1, MM74HC, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)