MM74HC163 Synchronous Clear Datasheet

MM74HC163 Datasheet, PDF, Equivalent


Part Number

MM74HC163

Description

Synchronous Binary Counter with Asynchronous Clear . Synchronous Binary Counter with Synchronous Clear

Manufacture

Fairchild

Total Page 8 Pages
Datasheet
Download MM74HC163 Datasheet


MM74HC163
September 1983
Revised February 1999
MM74HC161 • MM74HC163
Synchronous Binary Counter with Asynchronous Clear
• Synchronous Binary Counter with Synchronous Clear
General Description
The MM74HC161 and MM74HC163 synchronous presetta-
ble counters utilize advanced silicon-gate CMOS technol-
ogy and internal look-ahead carry logic for use in high
speed counting applications. They offer the high noise
immunity and low power consumption inherent to CMOS
with speeds similar to low power Schottky TTL. The HC161
and the HC163 are 4 bit binary counters. All flip-flops are
clocked simultaneously on the LOW-to-HIGH transition
(positive edge) of the CLOCK input waveform.
These counters may be preset using the LOAD input. Pre-
setting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held LOW counting is disabled
and the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken HIGH before the positive edge of CLOCK the count
operation will be unaffected.
All of these counters may be cleared by utilizing the
CLEAR input. The clear function on the MM74HC163
counter is synchronous to the clock. That is, the counters
are cleared on the positive edge of CLOCK while the clear
input is held LOW.
The MM74HC161 counter is cleared asynchronously.
When the CLEAR is taken LOW the counter is cleared
immediately regardless of the CLOCK.
Two active HIGH enable inputs (ENP and ENT) and a RIP-
PLE CARRY (RC) output are provided to enable easy cas-
cading of counters. Both ENABLE inputs must be HIGH to
count. The ENT input also enables the RC output. When
enabled, the RC outputs a positive pulse when the counter
overflows. This pulse is approximately equal in duration to
the HIGH level portion of the QA output. The RC output is
fed to successive cascaded stages to facilitate easy imple-
mentation of N-bit counters.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and ground.
Features
s Typical operating frequency: 40 MHz
s Typical propagation delay; clock to Q: 18 ns
s Low quiescent current: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Wide power supply range: 2–6V
Ordering Code:
Order Number Package Number
Package Description
MM74HC161M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC161MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC161N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC163SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC163MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC163N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS005008.prf
www.fairchildsemi.com

MM74HC163
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Tables
MM74HC161
CLK CLR
XL
XH
XH
XH
H
H
ENP ENT
XX
HL
LH
LL
XX
HH
Load
X
H
H
H
L
H
Function
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
MM74HC163
CLK CLR
L
XH
XH
XH
H
H
ENP ENT
XX
HL
LH
LL
XX
HH
Load
X
H
H
H
L
H
Function
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
H = HIGH Level
L = LOW Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
Logic Diagram
www.fairchildsemi.com
2


Features MM74HC161 • MM74HC163 Synchronous Bina ry Counter with Asynchronous Clear • Synchronous Binary Counter with Synchro nous Clear September 1983 Revised Febr uary 1999 MM74HC161 • MM74HC163 Sync hronous Binary Counter with Asynchronou s Clear • Synchronous Binary Counter with Synchronous Clear General Descript ion The MM74HC161 and MM74HC163 synchro nous presettable counters utilize advan ced silicon-gate CMOS technology and in ternal look-ahead carry logic for use i n high speed counting applications. The y offer the high noise immunity and low power consumption inherent to CMOS wit h speeds similar to low power Schottky TTL. The HC161 and the HC163 are 4 bit binary counters. All flip-flops are clo cked simultaneously on the LOW-to-HIGH transition (positive edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Presetting of all four flip-flops is synchronous to the rising edge of CLOCK. When LOAD is held LOW counting is disabled and the data on the A, B, C, and D inp.
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