TRI-STATE Transceiver. MM74HC245A Datasheet


MM74HC245A Transceiver. Datasheet pdf. Equivalent


MM74HC245A


Octal TRI-STATE Transceiver
MM54HC245A MM74HC245A Octal TRI-STATE Transceiver

January 1988

MM54HC245A MM74HC245A Octal TRI-STATE Transceiver
General Description
This TRI-STATE bidirectional buffer utilizes advanced silicon-gate CMOS technology and is intended for two-way asynchronous communication between data buses It has high drive current outputs which enable high speed operation even when driving large bus capacitances This circuit possesses the low power consumption and high noise immunity usually associated with CMOS circuitry yet has speeds comparable to low power Schottky TTL circuits This device has an active low enable input G and a direction control input DIR When DIR is high data flows from the A inputs to the B outputs When DIR is low data flows from the B inputs to the A outputs The MM54HC245A MM74HC245A transfers true data from one bus to the other This device can drive up to 15 LS-TTL Loads and does not have Schmitt trigger inputs All inputs are protected from damage due to static discharge by diodes to VCC and ground

Features
Y Y Y Y

Y Y

Typical propagation delay 13 ns Wide power supply range 2 – 6V Low quiescent current 80 mA maximum (74 HC) TRI-STATE outputs for connection to bus oriented systems High output drive 6 mA (minimum) Same as the ’645

Connection Diagram
Dual-In-Line Package

TL F 5165 – 1

Top View Order Number MM54HC245A or MM74HC245A

Truth Table
Control Inputs G L L ...



MM74HC245A
January 1988
MM54HC245A MM74HC245A
Octal TRI-STATE Transceiver
General Description
This TRI-STATE bidirectional buffer utilizes advanced sili-
con-gate CMOS technology and is intended for two-way
asynchronous communication between data buses It has
high drive current outputs which enable high speed opera-
tion even when driving large bus capacitances This circuit
possesses the low power consumption and high noise im-
munity usually associated with CMOS circuitry yet has
speeds comparable to low power Schottky TTL circuits
This device has an active low enable input G and a direction
control input DIR When DIR is high data flows from the A
inputs to the B outputs When DIR is low data flows from
the B inputs to the A outputs The MM54HC245A
MM74HC245A transfers true data from one bus to the oth-
er
Connection Diagram
This device can drive up to 15 LS-TTL Loads and does not
have Schmitt trigger inputs All inputs are protected from
damage due to static discharge by diodes to VCC and
ground
Features
Y Typical propagation delay 13 ns
Y Wide power supply range 2 – 6V
Y Low quiescent current 80 mA maximum (74 HC)
Y TRI-STATE outputs for connection to bus oriented
systems
Y High output drive 6 mA (minimum)
Y Same as the ’645
Dual-In-Line Package
Truth Table
Top View
Order Number MM54HC245A or MM74HC245A
Control
Inputs
G DIR
Operation
L L B data to A bus
L H A data to B bus
HX
Isolation
H e high level L e low level X e irrelevant
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 5165
TL F 5165 – 1
RRD-B30M105 Printed in U S A

MM74HC245A
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Voltage DIR and G pins (VIN)
DC Input Output Voltage (VIN VOUT)
Clamp Diode Current (ICD)
DC Output Current per pin (IOUT)
DC VCC or GND Current per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S O Package only
b0 5 to a7 0V
b1 5 to VCCa1 5V
b0 5 to VCCa0 5V
g20 mA
g35 mA
g70 mA
b65 C to a150 C
600 mW
500 mW
Lead Temp (TL) (Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN VOUT)
Operating Temp Range (TA)
MM74HC
MM54HC
Min
2
0
b40
b55
Input Rise Fall Times
(tr tf)
VCCe2 0V
VCCe4 5V
VCCe6 0V
Max
6
VCC
a85
a125
1000
500
400
Units
V
V
C
C
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC TAe25 C
Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C Units
Guaranteed Limits
VIH Minimum High Level Input
Voltage
2 0V
4 5V
6 0V
15
3 15
42
15
3 15
42
15 V
3 15 V
42 V
VIL Maximum Low Level Input
Voltage
2 0V
4 5V
6 0V
05
1 35
18
05
1 35
18
05 V
1 35 V
18 V
VOH
Minimum High Level Output VINeVIH or VIL
Voltage
lIOUTls20 mA
2 0V 2 0
4 5V 4 5
6 0V 6 0
19
44
59
19
44
59
19 V
44 V
59 V
VINeVIH or VIL
lIOUTls6 0 mA
lIOUTls7 8 mA
VOL Maximum Low Level Output VINeVIH or VIL
Voltage
lIOUTls20 mA
4 5V 4 2 3 98
6 0V 5 7 5 48
2 0V
4 5V
6 0V
0
0
0
01
01
01
3 84
5 34
01
01
01
37 V
52 V
01 V
01 V
01 V
IIN Input Leakage
Current (G and DIR)
VINeVIH or VIL
lIOUTls6 0 mA
lIOUTls7 8 mA
VINeVCC to GND
4 5V 0 2 0 26
6 0V 0 2 0 26
6 0V
g0 1
0 33
0 33
g1 0
04
04
g1 0
V
V
mA
IOZ Maximum TRI-STATE Output VOUTeVCC or GND 6 0V
Leakage Current
Enable GeVIH
g0 5
g5 0
g10
mA
ICC Maximum Quiescent Supply VINeVCC or GND 6 0V
Current
IOUTe0 mA
80
80
160 mA
Note 1 Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing
with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and
IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used
VIL limits are currently tested at 20% of VCC The above VIL specification (30%) of VCC) will be implemented no later than Q1 CY’89 O e VIL
2




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