MM74HC299 Shift Register Datasheet

MM74HC299 Datasheet, PDF, Equivalent


Part Number

MM74HC299

Description

8-Bit TRI-STATE Universal Shift Register

Manufacture

National

Total Page 7 Pages
Datasheet
Download MM74HC299 Datasheet


MM74HC299
January 1988
MM54HC299 MM74HC299
8-Bit TRI-STATE Universal Shift Register
General Description
This 8-bit TRI-STATE shift storage register utilizes advanced
silicon-gate CMOS technology Along with the low power
consumption and high noise immunity of standard CMOS
integrated circuits it has the ability to drive 15 LS-TTL
loads This circuit also features operating speeds compara-
ble to the equivalent low power Schottky device
The MM54HC299 MM74HC299 features multiplexed in-
puts outputs to achieve full 8-bit data handling in a single
20-pin package Due to the large output drive capability and
TRI-STATE feature this device is ideally suited for interfac-
ing with bus lines in a bus oriented system
Two function select inputs and two output control inputs are
used to choose the mode of operation as listed in the func-
tion table Synchronous parallel loading is accomplished by
taking both function select lines S0 and S1 high This places
the TRI-STATE outputs in a high impedance state which
permits data applied to the input output lines to be clocked
into the register Reading out of the register can be done
while the outputs are enabled in any mode A direct overrid-
ing CLEAR input is provided to clear the register whether
the outputs are enabled or disabled
The 54HC 74HC logic family is functionally as well as pinout
compatible with the standard 54LS 74LS logic family All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground
Features
Y Typical operating frequency 40 MHz
Y Typical propagation delay 20 ns
Y Low quiescent current 80 mA maximum (74HC)
Y High output drive for bus applications
Y Low quiescent current 1 mA maximum
Connection Diagram
Dual-In-Line Package
Order Number MM54HC299 or MM74HC299
TL F 5207 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 5207
RRD-B30M105 Printed in U S A

MM74HC299
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (ICD)
DC Output Current per pin (IOUT)
b0 5 to a7 0V
b1 5 to VCCa1 5V
b0 5 to VCCa0 5V
g20 mA
g25 mA (QA’ QH’)
g35 mA (others)
DC VCC or GND Current per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S O Package only
g70 mA
b65 C to a150 C
600 mW
500 mW
Lead Temp (TL) (Soldering 10 seconds)
260 C
DC Electrical Characteristics (Note 4)
Operating Conditions
Supply Voltage VCC
DC Input or Output Voltage
VIN VOUT
Operating Temp Range (TA)
MM HC
MM HC
Min
b
b
Input Rise or Fall Times
tr tf VCCe V
VCCe V
VCCe V
Max
VCC
a
a
Units
V
V
C
C
ns
ns
ns
Symbol
Parameter
Conditions
VCC TAe25 C
Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C Units
Guaranteed Limits
VIH Minimum High Level Input
Voltage
V
V
V
V
V
V
VIL Maximum Low Level Input
Voltage
V
V
V
V
V
V
VOH
Minimum High Level
Output Voltage
VINeVIH or VIL
lIOUTls mA
V
V
V
V
V
V
QA QH Outputs
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
A QA thru H QH Outputs
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
VOL Maximum Low Level
Output Voltage
VINeVIH or VIL
lIOUTls mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
QA and QH Outputs
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
V
V
V
V
V
A QA thru H QH Outputs
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
V
V
V
V
V
IIN
Maximum Input Current
VINeVCC or GND
V
g
g
g mA
IOZ Maximum TRI STATE Output VOUTeVCC or V g
GND
Leakage Currrent
GeVIH
g
g mA
ICC
Maximum Quiescent Supply VINeVCC or GND
V
Current
IOUTe mA
mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst-case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when
designing with this supply Worst-case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst-case leakage current (IIN
ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used
VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89
2


Features MM54HC299 MM74HC299 8-Bit TRI-STATE Univ ersal Shift Register January 1988 MM5 4HC299 MM74HC299 8-Bit TRI-STATE Univer sal Shift Register General Description This 8-bit TRI-STATE shift storage regi ster utilizes advanced silicon-gate CMO S technology Along with the low power c onsumption and high noise immunity of s tandard CMOS integrated circuits it has the ability to drive 15 LS-TTL loads T his circuit also features operating spe eds comparable to the equivalent low po wer Schottky device The MM54HC299 MM74H C299 features multiplexed inputs output s to achieve full 8-bit data handling i n a single 20-pin package Due to the la rge output drive capability and TRI-STA TE feature this device is ideally suite d for interfacing with bus lines in a b us oriented system Two function select inputs and two output control inputs ar e used to choose the mode of operation as listed in the function table Synchro nous parallel loading is accomplished b y taking both function select lines S0 and S1 high This places .
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