MM74HCT138 Line Decoder Datasheet

MM74HCT138 Datasheet, PDF, Equivalent


Part Number

MM74HCT138

Description

3-to-8 Line Decoder

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HCT138 Datasheet


MM74HCT138
February 1984
Revised February 1999
MM74HCT138
3-to-8 Line Decoder
General Description
The MM74HCT138 decoder utilizes advanced silicon-gate
CMOS technology, and are well suited to memory address
decoding or data routing applications. Both circuits feature
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet have speeds compara-
ble to low power Schottky TTL logic.
The MM74HCT138 have 3 binary select inputs (A, B, and
C). If the device is enabled these inputs determine which
one of the eight normally HIGH outputs will go LOW. Two
active LOW and one active HIGH enables (G1, G2A and
G2B) are provided to ease the cascading decoders.
The decoders’ output can drive 10 low power Schottky TTL
equivalent loads and are functionally and pin equivalent to
the 74LS138. All inputs are protected from damage due to
static discharge by diodes to VCC and ground.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s TTL input compatible
s Typical propagation delay: 20 ns
s Low quiescent current: 80 µA maximum (74HCT Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HCT138M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HCT138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT138MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT138N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
© 1999 Fairchild Semiconductor Corporation DS005362.prf
www.fairchildsemi.com

MM74HCT138
Truth Table
H = HIGH Level
L = LOW Level
X = Don’t Care
Note 1: G2 = G2A + G2B
Inputs
Outputs
Enable
Select
G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
(Note 1)
X H XXXHHHHHHHH
L X XXXHHHHHHHH
H L L L L LHHHHHHH
H L L LHHLHHHHHH
H L LHLHHLHHHHH
H L LHHHHHLHHHH
H L HL LHHHHLHHH
H L HLHHHHHHLHH
H L HHLHHHHHHLH
H L HHHHHHHHHHL
Logic Diagram
www.fairchildsemi.com
2


Features MM74HCT138 3-to-8 Line Decoder February 1984 Revised February 1999 MM74HCT138 3-to-8 Line Decoder General Descriptio n The MM74HCT138 decoder utilizes advan ced silicon-gate CMOS technology, and a re well suited to memory address decodi ng or data routing applications. Both c ircuits feature high noise immunity and low power consumption usually associat ed with CMOS circuitry, yet have speeds comparable to low power Schottky TTL l ogic. The MM74HCT138 have 3 binary sele ct inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one ac tive HIGH enables (G1, G2A and G2B) are provided to ease the cascading decoder s. The decoders’ output can drive 10 low power Schottky TTL equivalent loads and are functionally and pin equivalen t to the 74LS138. All inputs are protec ted from damage due to static discharge by diodes to VCC and ground. MM74HCT d evices are intended to interface between TTL and NMOS components .
Keywords MM74HCT138, datasheet, pdf, Fairchild, 3-to-8, Line, Decoder, M74HCT138, 74HCT138, 4HCT138, MM74HCT13, MM74HCT1, MM74HCT, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)