MM74HCT273 with Clear Datasheet

MM74HCT273 Datasheet, PDF, Equivalent


Part Number

MM74HCT273

Description

Octal D-Type Flip-Flop with Clear

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HCT273 Datasheet


MM74HCT273
February 1984
Revised February 1999
MM74HCT273
Octal D-Type Flip-Flop with Clear
General Description
The MM74HCT273 utilizes advanced silicon-gate CMOS
technology. It has an input threshold and output drive simi-
lar to LS-TTL with the low standby power of CMOS.
These positive edge-triggered flip-flops have a common
clock and clear-independent Q outputs. Data on a D input,
having the specified set-up and hold time, is transferred to
the corresponding Q output on the positive-going transition
of the clock pulse. The asynchronous clear forces all out-
puts LOW when it is LOW.
All inputs to this device are protected from damage due to
electrostatic discharge by diodes to VCC and ground.
MM74HCT devices are intended to interface TTL and
NMOS components to CMOS components. These parts
can be used as plug-in replacements to reduce system
power consumption in existing designs.
Features
s Typical propagation delay: 20 ns
s Low quiescent current: 80 µA maximum (74HCT series)
s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HCT273WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT273N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 1999 Fairchild Semiconductor Corporation DS005760.prf
www.fairchildsemi.com

MM74HCT273
Truth Table
Clear
L
H
H
H
H = HIGH Level (steady-state)
L = LOW Level (steady-state)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady-state input
conditions were established.
(Each Flip-Flop)
Inputs
Clock
X
L
D
X
H
L
X
Logic Diagram
Outputs
Q
L
H
L
Q0
www.fairchildsemi.com
2


Features MM74HCT273 Octal D-Type Flip-Flop with C lear February 1984 Revised February 19 99 MM74HCT273 Octal D-Type Flip-Flop w ith Clear General Description The MM74H CT273 utilizes advanced silicon-gate CM OS technology. It has an input threshol d and output drive similar to LS-TTL wi th the low standby power of CMOS. These positive edge-triggered flip-flops hav e a common clock and clear-independent Q outputs. Data on a D input, having th e specified set-up and hold time, is tr ansferred to the corresponding Q output on the positive-going transition of th e clock pulse. The asynchronous clear f orces all outputs LOW when it is LOW. A ll inputs to this device are protected from damage due to electrostatic discha rge by diodes to VCC and ground. MM74HC T devices are intended to interface TTL and NMOS components to CMOS components . These parts can be used as plug-in re placements to reduce system power consu mption in existing designs. Features s Typical propagation delay: 20 ns s Low quiescent current: 80 µ.
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