MM80C95 / Buffers Datasheet

MM80C95 Datasheet, PDF, Equivalent


Part Number

MM80C95

Description

TRI-STATE Hex Inverters / Buffers

Manufacture

National

Total Page 8 Pages
Datasheet
Download MM80C95 Datasheet


MM80C95
February 1988
MM70C95 MM80C95 MM70C97 MM80C97
TRI-STATE Hex Buffers
MM70C96 MM80C96 MM70C98 MM80C98
TRI-STATE Hex Inverters
General Description
These gates are monolithic complementary MOS (CMOS)
integrated circuits constructed with N- and P-channel en-
hancement mode transistors The MM70C95 MM80C95
and the MM70C97 MM80C97 convert CMOS or TTL out-
puts to TRI-STATE outputs with no logic inversion the
MM70C96 MM80C96 and the MM70C98 MM80C98 pro-
vide the logical opposite of the input signal The MM70C95
MM80C95 and the MM70C96 MM80C96 have common
TRI-STATE controls for all six devices The MM70C97
MM80C97 and the MM70C98 MM80C98 have two TRI-
STATE controls one for two devices and one for the other
four devices Inputs are protected from damage due to stat-
ic discharge by diode clamps to VCC and GND
Features
Y Wide supply voltage range
Y Guaranteed noise margin
Y High noise immunity
Y TTL compatible
Applications
Y Bus drivers
3 0V to 15V
1 0V
0 45 VCC (typ )
Drive 1 TTL Load
Typical propagation delay
into 150 pF load is 40 ns
Connection Diagrams (Dual-In-Line Packages)
MM70C95 MM80C95
MM70C96 MM80C96
Top View
TL F 5907 – 1
Order Number MM70C95 or MM80C95
MM70C97 MM80C97
Top View
TL F 5907 – 2
Order Number MM70C96 or MM80C96
MM70C98 MM80C98
Top View
TL F 5907 – 3
Order Number MM70C97 or MM80C97
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 5907
Top View
TL F 5907 – 4
Order Number MM70C98 or MM80C98
RRD-B30M105 Printed in U S A

MM80C95
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
Operating Temperature Range
MM70CXX
MM80CXX
b0 3V to VCC a 0 3V
b55 C to a125 C
b40 C to a85 C
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line
Small Outline
Power Supply Voltage (VCC)
Lead Temperature
(Soldering 10 seconds)
b65 C to a150 C
700 mW
500 mW
18V
260 C
DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min Typ Max Units
CMOS TO CMOS
VIN(1)
Logical ‘‘1’’ Input Voltage
VIN(0)
Logical ‘‘0’’ Input Voltage
VOUT(1) Logical ‘‘1’’ Output Voltage
VOUT(0) Logical ‘‘0’’ Output Voltage
IIN(1)
IIN(0)
IOZ
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Output Current in High
Impedance State
ICC Supply Current
TTL INTERFACE
VCC e 5V
VCC e 10V
VCC e 5V
VCC e 10V
VCC e 5V
VCC e 10V
VCC e 5V
VCC e 10V
VCC e 15V
VCC e 15V VO e 15V
VCC e 15V VO e 0V
VCC e 15V
35
80
45
90
b1 0
b1 0
15
20
0 005
b0 005
0 005
b0 005
0 01
05
10
10
10
15
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
VIN(1)
Logical ‘‘1’’ Input Voltage
70C VCC e 4 5V
80C VCC e 4 75V
VCC b 1 5
VCC b 1 5
VIN(0)
Logical ‘‘0’’ Input Voltage
70C VCC e 4 5V
80C VCC e 4 75V
VOUT(1)
Logical ‘‘1’’ Output Voltage 70C VCC e 4 5V IO e b1 6 mA
80C VCC e 4 75V IO e b1 6 mA
24
24
VOUT(0)
Logical ‘‘0’’ Output Voltage 70C VCC e 4 5V IO e 1 6 mA
80C VCC e 4 75V IO e 1 6 mA
OUTPUT DRIVE (Short Circuit Current)
V
V
08 V
08 V
V
V
04 V
04 V
ISOURCE Output Source Current
VCC e 5V VIN(1) e 5V
TA e 25 C VOUT e 0V
b4 35
mA
ISOURCE Output Source Current
VCC e 10V VIN(1) e 10V
TA e 25 C VOUT e 0V
b20
mA
ISINK
Output Sink Current
VCC e 5V VIN(0) e 0V
TA e 25 C VOUT e VCC
4 35
mA
ISINK
Output Sink Current
VCC e 10V VIN(0) e 0V
TA e 25 C VOUT e VCC
20
mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the device should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 Capacitance is guaranteed by periodic testing
Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
2


Features MM70C95 MM80C95 MM70C97 MM80C97 TRI-STAT E Hex Buffers MM70C96 MM80C96 MM70C98 M M80C98 TRI-STATE Hex Inverters Februar y 1988 MM70C95 MM80C95 MM70C97 MM80C97 TRI-STATE Hex Buffers MM70C96 MM80C96 MM70C98 MM80C98 TRI-STATE Hex Inverters General Description These gates are mo nolithic complementary MOS (CMOS) integ rated circuits constructed with N- and P-channel enhancement mode transistors The MM70C95 MM80C95 and the MM70C97 MM8 0C97 convert CMOS or TTL outputs to TRI -STATE outputs with no logic inversion the MM70C96 MM80C96 and the MM70C98 MM8 0C98 provide the logical opposite of th e input signal The MM70C95 MM80C95 and the MM70C96 MM80C96 have common TRI-STA TE controls for all six devices The MM7 0C97 MM80C97 and the MM70C98 MM80C98 ha ve two TRISTATE controls one for two de vices and one for the other four device s Inputs are protected from damage due to static discharge by diode clamps to VCC and GND Features Y Y Y Y Wide sup ply voltage range Guaranteed noise margin High noise immunity T.
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