93L28 Data Sheet PDF | National Semiconductor





(Datasheet) 93L28 PDF Download

Part Number 93L28
Description Dual 8-Bit Shift Register
Manufacture National Semiconductor
Total Page 6 Pages
PDF Download Download 93L28 Datasheet PDF

Features: 93L28 Dual 8-Bit Shift Register June 19 89 93L28 Dual 8-Bit Shift Register Gen eral Description The 93L28 is a high sp eed serial storage element providing 16 bits of storage in the form of two 8-b it registers The multifunctional capabi lity of this device is provided by seve ral features 1) additional gating is pr ovided at the input to both shift regis ters so that the input is easily multip lexed between two sources 2) the clock of each register may be provided separa tely or together 3) both the true and c omplementary outputs are provided from each 8-bit register and both registers may be master cleared from a common inp ut Features Y Y Y Y 2-input multiple xer provided at data input of each regi ster Gated clock input circuitry Both t rue and complementary outputs provided from last bit of each register Asynchro nous master reset common to both regist ers Connection Diagram Dual-In-Line Pa ckage Logic Symbol TL F 10200 – 1 Order Number 93L28DMQB or 93L28FMQB See NS Package Number J16A or.

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93L28 datasheet
June 1989
93L28
Dual 8-Bit Shift Register
General Description
The 93L28 is a high speed serial storage element providing
16 bits of storage in the form of two 8-bit registers The
multifunctional capability of this device is provided by sever-
al features 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources 2) the clock of each register may be
provided separately or together 3) both the true and com-
plementary outputs are provided from each 8-bit register
and both registers may be master cleared from a common
input
Features
Y 2-input multiplexer provided at data input of each
register
Y Gated clock input circuitry
Y Both true and complementary outputs provided from
last bit of each register
Y Asynchronous master reset common to both registers
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10200 – 1
Order Number 93L28DMQB or 93L28FMQB
See NS Package Number J16A or W16A
VCC e Pin 16
GND e Pin 8
Pin
Names
S
D0 D1
CP
MR
Q7
Q7
Description
Data Select Input
Data Inputs
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
Master Reset Input (Active LOW)
Last Stage Output
Complementary Output
TL F 10200 – 2
C1995 National Semiconductor Corporation TL F 10200
RRD-B30M105 Printed in U S A

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