embedded processor. PR31100 Datasheet

PR31100 processor. Datasheet pdf. Equivalent

Part PR31100
Description Highly integrated embedded processor
Feature .
Manufacture Philips
Datasheet
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PR31100
INTEGRATED CIRCUITS
MIPS
PR31100
Highly integrated embedded processor
Preliminary specification
Version 1.2
1996 Aug 07
Philips
Semiconductors



PR31100
Philips Semiconductors
Preliminary specification
Highly integrated embedded processor
MIPS
PR31100
Version 1.2
GENERAL DESCRIPTION
PR31100 Processor is a single-chip, low-cost, integrated embedded
processor consisting of MIPS R3000 core and system support logic
to interface with various types of devices.
PR31100 consists of a MIPS R3000 RISC CPU with 4 KBytes of
instruction cache memory and 1 KByte of data cache memory, plus
integrated functions for interfacing to numerous system components
and external I/O modules. The R3000 RISC CPU is also augmented
with a multiply/accumulate module to allow integrated DSP
functions, such as a software modem for high-performance standard
data and fax protocols. PR31100 also contains multiple DMA
channels and a high-performance and flexible Bus Interface Unit
(BIU) for providing an efficient means for transferring data between
external system memory, cache memory, the CPU core, and
external I/O modules. The types of external memory devices
supported include dynamic random access memory (DRAM),
synchronous dynamic random access memory (SDRAM), static
random access memory (SRAM), Flash memory, read-only memory
(ROM), and expansion cards (PCMCIA and/or MagicCard).
PR31100 also contains a System Interface Module (SIM) containing
integrated functions for interfacing to numerous external I/O
modules such as liquid crystal displays (LCDs), the UCB1100 (which
handles most of the analog functions of the system, including sound
and telecom codecs and touchscreen ADC), ISDN/high-speed
serial, infrared, wireless peripherals, Magicbus, etc. Lastly, PR31100
contains support for implementation of power management,
whereby various PR31100 internal modules and external
subsystems can be individually (under software control) powered up
and down.
Figure 1 shows an External Block Diagram of PR31100.
FEATURES
32-bit R3000 RISC static CMOS CPU
4 KByte instruction cache
1 KByte data cache
Multiply/accumulator
On-chip peripherals with individual power-down
Multi-channel DMA controller
Bus interface unit
Memory controller for ROM, Flash, RAM, DRAM, SDRAM,
SRAM, and PCMCIA and/or MagicCard
Power management module
Video module
Real-time clock 32.760KHz reference
High-speed serial interface
Infrared module
Dual-UART
SPI bus
3.3V supply voltage
208-pin LQFP (Low profile quad flat pack)
40MHz operation frequency
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE (°C) AND PACKAGE
PR31100ABC
0 to +70, 208-pin Low Profile Quad Flat Pack
FREQUENCY
(MHz)
40
DRAWING NUMBER
LQFP208
1996 Aug 07
2





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