INSULATED TYPE. PS21312 Datasheet

PS21312 TYPE. Datasheet pdf. Equivalent


Mitsubishi Electric Semiconductor PS21312
PS21312
MITMSUITBSIUSBHISSHEIMSIECMOINCDOUNCDTUOCRTO<RDu<aDl-uIna-lL-Iinn-eLiPnaecPkacgkeaIgneteIlnlitgeellnigtePnotwPeorwMeor dMuoled>ule>
PS21PS32112312
TRATNRSAFNESRF-EMRO-MLDOLTDYPTEYPE
INSIUNLSAUTLEADTETDYPTEYPE
INTEGRATED POWER FUNCTIONS
3rd generation IGBT inverter bridge for 3 phase DC-to-AC
power conversion.
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection.
Note : Bootstrap supply scheme can be applied.
• For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short-circuit protection (SC).
• Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side IGBT).
• Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit.
APPLICATION
AC200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
HEAT SINK SIDE
(3.556)
(3.556)
(1.656)
TERMINAL CODE
(1) TERMINAL
(0.5)
(0.5)
1 VUFS
2 (UPG)
3 VUFB
4 VP1
5 (COM)
PCB
6 UP
(1) PATTERN 7 VVFS
(1)
(0.5)
(1.8MIN)
(1.9) SLIT
8 (VPG)
9 VVFB
(PCB LAYOUT)
10 VP1
(1.778 × 26)
DUMMY PIN
Detail A
11 (COM)
*Note2 12 VP
(1.778)
(6.25) (6.25) (6.25) (8)
(8)
A
(5)
13 VWFS
14 (WPG)
15 VWFB
28 27 26 25 24 23 22 21 20 19 18 16 15 13 12 10 9 8 7 6 5 4
17 14 11
321
(φ2 DEPTH 2)
29
30
Type name , Lot No.
(φ3.3)
16 VP1
17 (COM)
18 WP
19 (UNG)
20 VNO(NC)
21 UN
22 VN
HEAT SINK SIDE
23 WN
(35°)
24 FO
25 CFO
26 CIN
27 VNC
35 34 33 32 31
28 VN1
29 (WNG)
30 (VNG)
(7.62)
(4MIN)
31 P
32 U
(7.62 × 4)
(1.25)
33 V
(41)
(2.5)
34 W
35 N
(42)
(49) *Note1:(***) = Dummy Pin.
*Note 2: In order to increase the surface distance between terminals, cut a slit, etc. on the PCB surface
when mounting a module.
* Note: The values used in the above figure are tentative.
Aug. 1999


PS21312 Datasheet
Recommendation PS21312 Datasheet
Part PS21312
Description TRANSFER-MOLD TYPE INSULATED TYPE
Feature PS21312; MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR
Manufacture Mitsubishi Electric Semiconductor
Datasheet
Download PS21312 Datasheet




Mitsubishi Electric Semiconductor PS21312
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21312
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
C3 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C4 : 0.22~2µF R-category ceramic capacitor for noise filtering.
Inrush current
limiter circuit
High-side input (PWM)
(5V line) Note 1,2)
Input signal Input signal Input signal
coditioning coditioning coditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
Protection
circuit (UV)
Protection
circuit (UV)
Drive circuit Drive circuit Drive circuit
P
Bootstrap circuit
For detailed description
C4 of the boot-strap circuit
C3 construction, please
contact Mitsubishi
Electric
(Note 6)
DIP-IPM
AC input
C
Z
Z : Surge absorber
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Protection against common-mode noise)
(Note 4)
Fig. 3
N1
VNC
N
CIN
Drive circuit
Input signal conditioning Fo logic
SC
protection
H-side IGBTS
U
V
W
M
AC line output
L-side IGBTS
Control supply
Under-Voltage
protection
Note1:
2:
3:
4:
5:
6:
Low-side input (PWM)
FO CFO
(5V line) (Note 1, 2) FO output (5V line)
(Note 3, 5)
VNC
VD
To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6)
(15V line)
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 6)
This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kresistance.
(see also Fig. 6)
The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P and N1 DC power input terminals.
Fo output pulse width should be decided by connecting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.))
High voltage diodes (600V or more) should be used in the bootstrap circuit.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
P
Drive circuit
External protection circuit
H-side IGBTS
L-side IGBTS
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection
U Trip Level
V
W
N1
Shunt Resistor
AN
Note1:
2:
CR
C
VNC
CIN
B
Drive circuit
Protection circuit
In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
0
Collector current
waveform
2 tw (µs)
Aug. 1999



Mitsubishi Electric Semiconductor PS21312
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21312
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Condition
Applied between P-N
Applied between P-N
TC = 25°C
TC = 25°C, instantaneous value (pulse)
TC = 25°C, per 1 chip
(Note 1)
Ratings
450
500
600
5
10
20
–20~+150
Unit
V
V
V
A
A
W
°C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf 100°C). However, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125°C (@ Tf 100°C).
CONTROL (PROTECTION) PART
Symbol
VD
VDB
Parameter
Control supply voltage
Control supply voltage
VCIN
VFO
IFO
VSC
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP-VNC, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Ratings
20
20
–0.5~+5.5
–0.5~VD+0.5
15
–0.5~VD+0.5
Unit
V
V
V
V
mA
V
TOTAL SYSTEM
Symbol
Parameter
VCC(PROT) Self protection supply voltage limit
(short-circuit protection capability)
Tf Heat-fin operation temperature
Tstg Storage temperature
Viso Isolation voltage
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Ratings
400
–20~+100
–40~+125
1500
Unit
V
°C
°C
Vrms
Note 2 : Tf MEASUREMENT POINT
Al Board Specifications:
Dimensions 100 × 100 × 10mm, finishing: 12s, warp: –50~100µm
Control Terminals
18mm
16mm
FWDi Chip
Al Board
IGBT/FWDi Chip
IGBT Chip
Groove
Temp. measurement
point
(inside the Al board)
N W VUP
Power Terminals
100~200µm of evenly applied Silicon-Grease
Temp. measurement point
(inside the Al board)
Aug. 1999





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