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Hardware Specifications. MPC860 Datasheet

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Hardware Specifications. MPC860 Datasheet
















MPC860 Specifications. Datasheet pdf. Equivalent













Part

MPC860

Description

Hardware Specifications



Feature


Hardware Specification MPC860EC/D Rev. 6.1, 11/2002 MPC860 Family Hardware Spe cifications This document contains de tailed information on power considerati ons, DC/AC electrical characteristics, and AC timing specifications for the M PC860 family. This document contains th e following topics: Topic Page Part I, “Overview” Part II, “Features” Part III, “Maximum Tolerated Ra.
Manufacture

Motorola

Datasheet
Download MPC860 Datasheet


Motorola MPC860

MPC860; tings” Part IV, “Thermal Characteris tics” Part V, “Power Dissipation” Part VI, “DC Characteristics” Part VII, “Thermal Calculation and Measur ement” Part VIII, “Layout Practices ” Part IX, “Bus Signal Timing” Pa rt X, “IEEE 1149.1 Electrical Speci cations” Part XI, “CPM Electrical Characteristics” Part XII, “UTOPIA AC Electrical Specifications” Part XIII, “FEC Electrical .


Motorola MPC860

Characteristics” Part XIV, “Mechanic al Data and Ordering Information” Par t XV, “Document Revision History” 1 2 6 7 8 9 10 13 13 41 43 65 66 70 74 Part I Overview The MPC860 Quad Integr ated Communications Controller (PowerQU ICC™) is a versatile one-chip integra ted microprocessor and peripheral combi nation designed for a variety of contro ller applications. It particul.


Motorola MPC860

arly excels in both communications and n etworking systems. The PowerQUICC unit is referred to as the MPC860 in this ma nual. The MPC860 is a derivative of Mot orola’s MC68360 Quad Integrated Commu nications Controller (QUICC™), referr ed to here as the QUICC, that implement s the PowerPC architecture. The CPU on the MPC860 is a 32-bit Features MPC8x x core that incorporat.





Part

MPC860

Description

Hardware Specifications



Feature


Hardware Specification MPC860EC/D Rev. 6.1, 11/2002 MPC860 Family Hardware Spe cifications This document contains de tailed information on power considerati ons, DC/AC electrical characteristics, and AC timing specifications for the M PC860 family. This document contains th e following topics: Topic Page Part I, “Overview” Part II, “Features” Part III, “Maximum Tolerated Ra.
Manufacture

Motorola

Datasheet
Download MPC860 Datasheet




 MPC860
Hardware Specification
MPC860EC/D
Rev. 6.1, 11/2002
MPC860 Family
Hardware Specifications
This document contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications for the MPC860 family.
This document contains the following topics:
Topic
Part I, “Overview”
Part II, “Features”
Part III, “Maximum Tolerated Ratings”
Part IV, “Thermal Characteristics”
Part V, “Power Dissipation”
Part VI, “DC Characteristics”
Part VII, “Thermal Calculation and Measurement”
Part VIII, “Layout Practices”
Part IX, “Bus Signal Timing”
Part X, “IEEE 1149.1 Electrical Specifications”
Part XI, “CPM Electrical Characteristics”
Part XII, “UTOPIA AC Electrical Specifications”
Part XIII, “FEC Electrical Characteristics”
Part XIV, “Mechanical Data and Ordering Information”
Part XV, “Document Revision History”
Page
1
2
6
7
8
9
10
13
13
41
43
65
66
70
74
Part I Overview
The MPC860 Quad Integrated Communications Controller (PowerQUICC™)
is a versatile one-chip integrated microprocessor and peripheral combination
designed for a variety of controller applications. It particularly excels in both
communications and networking systems. The PowerQUICC unit is referred to
as the MPC860 in this manual.
The MPC860 is a derivative of Motorola’s MC68360 Quad Integrated
Communications Controller (QUICC), referred to here as the QUICC, that
implements the PowerPC architecture. The CPU on the MPC860 is a 32-bit




 MPC860
Features
MPC8xx core that incorporates memory management units (MMUs) and instruction and
data caches and that implements the PowePC instruction set. The communications
processor module (CPM) from the MC68360 QUICC has been enhanced by the addition of
the inter-integrated controller (I2C) channel. The memory controller has been enhanced,
enabling the MPC860 to support any type of memory, including high-performance
memories and new types of DRAMs. A PCMCIA socket controller supports up to two
sockets. A real-time clock has also been integrated.
Table 1 shows the functionality supported by the members of the MPC860 family.
Table 1. MPC860 Family Functionality
Cache (Kbytes)
Ethernet
Part
Instruction
Cache
Data Cache
10T
10/100
ATM
SCC
MPC860DE
4
4
Up to 2
2
MPC860DT
4
4
Up to 2
1
yes
2
MPC860DP
16
8
Up to 2
1
yes
2
MPC860EN
4
4
Up to 4
4
MPC860SR
4
4
Up to 4
yes
4
MPC860T
4
4
Up to 4
1
yes
4
MPC860P
16
8
Up to 4
1
yes
4
MPC855T 4 4 1 1 yes 1
1 Supporting documentation for these devices refers to the following:
1. MPC860 PowerQUICC User’s Manual (MPC860UM/D, Rev. 1).
2. MPC8XX ATM Supplement (MPC860SARUM/AD).
3. MPC860T (Rev. D), Fast Ethernet Controller Supplement (MPC860TREVDSUPP).
4. MPC855T User’s Manual (MPC855TUM/D, Rev. 1).
Ref. 1
1
1,2,3
1,2,3
1
1,2
1,2,3
1,2,3
4
Part II Features
The following list summarizes the key MPC860 features:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without
conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets;
4-Kbyte instruction caches are two-way, set-associative with 128 sets.
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data
caches are two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit
(4-word) cache blocks.
2
MPC860 Family Hardware Specifications
MOTOROLA




 MPC860
Features
– Caches are physically addressed, implement a least recently used (LRU)
replacement algorithm, and are lockable on a cache block basis.
— Instruction and data caches are two-way, set-associative, physically addressed,
LRU replacement, and lockable on-line granularity.
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16
virtual address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Operates at up to 80 MHz
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and
other memory devices.
— DRAM controller programmable to support most size and speed memory
interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte to 256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
• General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
• System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
MOTOROLA
MPC860 Family Hardware Specifications
3




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