DatasheetsPDF.com

RAM SRAM. NTE6508 Datasheet

DatasheetsPDF.com

RAM SRAM. NTE6508 Datasheet
















NTE6508 SRAM. Datasheet pdf. Equivalent













Part

NTE6508

Description

Integrated Circuit CMOS / 1K Static RAM (SRAM)



Feature


NTE6508 Integrated Circuit CMOS, 1K Stat ic RAM (SRAM) Description: The NTE6508 is a 1024 x 1 fully static CMOS RAM in a 16–Lead DIP type package fabricated using self–aligned silicon gate tech nology. Synchronous circuit design tech niques are employed to acheive high per formance and low power operation. On ch ip latches are provided for address all owing effecient interf.
Manufacture

NTE Electronics

Datasheet
Download NTE6508 Datasheet


NTE Electronics NTE6508

NTE6508; acing with microprocessor systems. The d ata output buffers can be forced to a h igh impedance state for use in expanded memory arrays. Features: D Low Power S tandby: 50µW Max D Low Power Operation : 20mW/MHz Max D Fast Access Time: 300n s Max D Data Retention: 2V Min D TTL Co mpatible Input/Output D High Output Dri ve: 2 TTL Loads D On–Chip Address Reg ister Absolute Maximu.


NTE Electronics NTE6508

m Ratings: (Note 1) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V Input, Output or I/ O Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.3V to VCC +0.3V Typi cal Derating Factor . . . . . . . . . . . . . . . . . . . ..


NTE Electronics NTE6508

. . . . . . . . . . . . . . . . . 1.5mA /MHz increase in ICC(OP) Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925 Gates Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 °C Storage Tempera.





Part

NTE6508

Description

Integrated Circuit CMOS / 1K Static RAM (SRAM)



Feature


NTE6508 Integrated Circuit CMOS, 1K Stat ic RAM (SRAM) Description: The NTE6508 is a 1024 x 1 fully static CMOS RAM in a 16–Lead DIP type package fabricated using self–aligned silicon gate tech nology. Synchronous circuit design tech niques are employed to acheive high per formance and low power operation. On ch ip latches are provided for address all owing effecient interf.
Manufacture

NTE Electronics

Datasheet
Download NTE6508 Datasheet




 NTE6508
NTE6508
Integrated Circuit
CMOS, 1K Static RAM (SRAM)
Description:
The NTE6508 is a 1024 x 1 fully static CMOS RAM in a 16–Lead DIP type package fabricated using
self–aligned silicon gate technology. Synchronous circuit design techniques are employed to acheive
high performance and low power operation. On chip latches are provided for address allowing effeci-
ent interfacing with microprocessor systems. The data output buffers can be forced to a high imped-
ance state for use in expanded memory arrays.
Features:
D Low Power Standby: 50µW Max
D Low Power Operation: 20mW/MHz Max
D Fast Access Time: 300ns Max
D Data Retention: 2V Min
D TTL Compatible Input/Output
D High Output Drive: 2 TTL Loads
D On–Chip Address Register
Absolute Maximum Ratings: (Note 1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA/MHz increase in ICC(OP)
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925 Gates
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Lead Temperature (During Soldering, 10s max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Note 1. Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress only rating and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not im-
plied. This device is sensitive to electrostatic discharge, users should follow proper IC han-
dling procedures.
Recommended Operating Conditions:
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40° to +85°C




 NTE6508
DC Electrical Characteristics: VCC = 5V ±10%, TA = 40° to +85°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Standby Supply Current
Operating Supply Current
Data Retention Supply Current
Data Retention Supply Voltage
Input Leakage Current
Output Leakage Current
Input Voltage, LOW
Input Voltage, HIGH
Output Voltage, LOW
Output Voltage, HIGH
ICC(SB)
ICC(OP)
ICC(DR)
VCC(DR)
II
IOZ
VIL
VIH
VOL
VOH
IO = 0, VI = VCC or GND, VCC = 5V
E = 1MHz, IO = 0, VI = VCC or GND,
VCC = 5.5V, Note 2
VCC = 2V, IO = 0, VI = VCC or GND,
E = VCC
VI = VCC or GND, VCC = 5.5V
VO = VCC or GND, VCC = 5.5V
VCC = 4.5V
VCC = 5.5V
IO = 3.2mA, VCC = 4.5V
IO = 0.4mA, VCC = 4.5V
2.0
1.0
1.0
0.3
VCC2
2.4
10 µA
4 mA
10 µA
––V
+1.0 µA
+1.0 µA
+0.8 V
VCC+0.3 V
0.4 V
––V
Note 2. Typical derating 1.5mA/MHz increase in ICC(OP).
Capacitance: (TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Input Capacitance
Output Capacitance
CI f = 1MHz, All measurements are ref-
CO erenced to device GND
6 pF
10 pF
AC Electrical Characteristics: VCC = 5V ±10%, TA = 40° to +85°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Chip Enable Access Time
TELQV Note 3, Note 5
– – 300 ns
Address Access Time
TAVQV Note 3, Note 5, & Note 6
– – 300 ns
Chip Enable Output Enable Time
TELQX Note 4, Note 5
5 160 ns
Write Enable Output Disable Time
TWLQZ Note 4, Note 5
– – 160 ns
Chip Enable Output Disable Time
TEHQZ Note 4, Note 5
– – 160 ns
Chip Enable Pulse Negative Width
TELEH Note 3, Note 5
300
ns
Chip Enable Pulse Positive Width
TEHEL Note 3, Note 5
100
ns
Address Setup Time
TAVEL Note 3, Note 5
0 – – ns
Address Hold Time
TELAX Note 3, Note 5
50
ns
Data Setup Time
TDVWH Note 3, Note 5
110
ns
Data Hold Time
TWHDX Note 3, Note 5
0 – – ns
Chip Enable Write Pulse Setup Time TWLEH Note 3, Note 5
130
ns
Chip Enable Write Pulse Hold Time TELWH Note 3, Note 5
130
ns
Write Enable Pulse Width
TWLWH Note 3, Note 5
130
ns
Read or Write Cycle Time
TELEL Note 3, Note 5
350
ns
Note 3. Input pulse levels: 0.8V to VCC 2V; Input rise and fall times: 5ns (max); Input and output
timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) for CL
greater than 50pF, access time is derated by 0.15ns per pF.
Note 4. Tested at initial design and after major design changes.
Note 5. VCC = 4.5V and 5.5V.
Note 6. TAVQV = TELQV + TAVEL.




 NTE6508
Read Cycle Truth Table:
Time Reference
1
0
1
2
3
4
5
E
H
L
L
H
Inputs
WA
XX
HV
HX
HX
HX
XX
HV
Outputs
DQ
Function
X Z Memory Disabled
X Z Cycle Begins, Addresses are Latched
X X Output Enables
X V Output Valid
X V Read Accomplished
X Z Prepare for Next Cycle (Same as 1)
X Z Cycle Ends, Next Cycle Begins (Same as 0)
In the NTE6508 Read Cycle, the address information is latched into the on chip registers on the falling
edge of E (T = 0). Minimum address setup and hold time requirements must be met. After the required
hold time, the addresses may change state without affecting device operation. During time (T = 1)
the data output becomes enabled; however, the data is not valid until during time (T = 2). W must
remain high for the read cycle. After the output data has been read, E may return high (T = 3). This
will disable the chip and force the output buffer to a high impedance state. After the required E high
time (TEHEL) the RAM is ready for the next memory cycle (T = 4).
Write Cycle Truth Table:
Time Reference
1
0
1
2
3
4
5
E
H
L
L
H
Inputs
WA
XX
XV
X
X
HX
XX
XV
Outputs
DQ
Function
X Z Memory Disabled
X Z Cycle Begins, Addresses are Latched
X Z Write Period Begins
V Z Data is Written
X Z Write Completed
X Z Prepare for Next Cycle (Same as 1)
X Z Cycle Ends, Next Cycle Begins (Same as 0)
The write cycle is initiated by the falling edge of E which latches the address information into the on
chip registers. The write portion of the cycle is defined as both E and W being low simultaneously.
W may go low anytime during the cycle provided that the write enable pulse setup time (TWLEH) is
met. The write portion of the cycle is terminated by the first rising edge of either E or W. Data setup
and hold times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed, the W line may remain low until all desired
locations have been written. When this method is used, data setup and hold times must be referenced
to the rising edge of E. By positioning the W pulse at different times within the E low time (TELEH),
various types of write cycles may be performed.
If the E low time (TELEH) is greater than the W pulse (TWLWH) plus an output enable time (TELQX),
a combination read write cycle is executed. Data may be modified an indefinite number of times dur-
ing any write cycle (TELEH). The data input and data output pins may be tied together for use with
a common I/O data bus structure. When using the RAM in this method allow a minimum of one output
disable time (TWLQZ) after W goes low before applying input data to the bus. This will insure that
the output buffers are not active.




Recommended third-party NTE6508 Datasheet







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)