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Sync System. NTE849 Datasheet

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Sync System. NTE849 Datasheet
















NTE849 System. Datasheet pdf. Equivalent













Part

NTE849

Description

Integrated Circuit TV Horizontal/Vertical Countdown Digital Sync System



Feature


NTE849 Integrated Circuit TV Horizontal/ Vertical Countdown Digital Sync System Description: The NTE849 is an integrate d circuit in a 14–Lead DIP type packa ge designed for use in TV horizontal/ v etical countdown digital sync systems. In some video playback units, there are incorrect frequency relationships betw een horizontal and field frequencies. A utomatic forced asyn.
Manufacture

NTE Electronics

Datasheet
Download NTE849 Datasheet


NTE Electronics NTE849

NTE849; chronous mode eliminates jitter when equ alizer pulses are correct, but these in correct frequency relationships exist. Automatic standard mode occurs upon det ection of nine or more equalizing pulse s during a six–line– width vertical driving period after seven fields of c oincidence between integrated vertical (IV) sync and internal counter output. Standard mode is retai.


NTE Electronics NTE849

ned for seven fields of missing or mutil ated vertical sync pulses. If two or mo re noise pulses are detected at Pin12 d uring a 384–line active scan time, a noise detector reverts the system to st andard mode at the next field of coinci dence (without seven fields of coincide ne delay). Thus, the unit stays in stan dard mode during tuner channel changes. An automatic mode–r.


NTE Electronics NTE849

ecognition system places the unit in sta ndard mode for NTSC signals or into non –synchronous mode for non–standard sync signals. An external oscillator (N TE701) supplies an input to Pin9 that i s 32 times the horizontal rate. An inte rnal divide–by–16 counter converts this input (32fH) to 2fH for use elsewh ere. This 32fH signal is further divide d to fH, which is availabl.





Part

NTE849

Description

Integrated Circuit TV Horizontal/Vertical Countdown Digital Sync System



Feature


NTE849 Integrated Circuit TV Horizontal/ Vertical Countdown Digital Sync System Description: The NTE849 is an integrate d circuit in a 14–Lead DIP type packa ge designed for use in TV horizontal/ v etical countdown digital sync systems. In some video playback units, there are incorrect frequency relationships betw een horizontal and field frequencies. A utomatic forced asyn.
Manufacture

NTE Electronics

Datasheet
Download NTE849 Datasheet




 NTE849
NTE849
Integrated Circuit
TV Horizontal/Vertical Countdown
Digital Sync System
Description:
The NTE849 is an integrated circuit in a 14–Lead DIP type package designed for use in TV horizontal/
vetical countdown digital sync systems. In some video playback units, there are incorrect frequency
relationships between horizontal and field frequencies. Automatic forced asynchronous mode elimi-
nates jitter when equalizer pulses are correct, but these incorrect frequency relationships exist.
Automatic standard mode occurs upon detection of nine or more equalizing pulses during a six–line–
width vertical driving period after seven fields of coincidence between integrated vertical (IV) sync and
internal counter output. Standard mode is retained for seven fields of missing or mutilated vertical
sync pulses.
If two or more noise pulses are detected at Pin12 during a 384–line active scan time, a noise detector
reverts the system to standard mode at the next field of coincidence (without seven fields of coinci-
dene delay). Thus, the unit stays in standard mode during tuner channel changes.
An automatic mode–recognition system places the unit in standard mode for NTSC signals or into
non–synchronous mode for non–standard sync signals.
An external oscillator (NTE701) supplies an input to Pin9 that is 32 times the horizontal rate. An inter-
nal divide–by–16 counter converts this input (32fH) to 2fH for use elsewhere. This 32fH signal is further
divided to fH, which is available at Pin11 to drive the horizontal deflection circuits. A divide–by–525
counter further divides the 2fH signal to generate the vertical ramp generator timing pulses and the
vertical blanking pulse.
A phasing circuit (part of the mode recognition and vertical regeneration circuits) insures that the 525
counter is reset in coincidence with the vertical sync. It does this by comparing the internally gener-
ated vertical pulse with an extrnal integrated vertical sync signal applied to Pin12. The automatic
mode recognition circuit forces the NTE849 into the standard mode for NTSC signals or into the non–
synchronous mode for non–standard sync signals such as video games. An input control signal (or
no connection) at Pin8 places the NTE849 into non–synchronous operation.
A phasing and timing logic circuit checks to see if the line counter is in sync with the IV signal at Pin12.
Seven consecutive fields of in–phase coincidence with the IV signal are needed to achieve standard
mode in unless two or more noise pulses are de–detected at input Pin12 during the active scan time.
In this case, normal mode will be acquired in one field.




 NTE849
Description (Cont’d):
In the standard divideby525 mode, the integrated vertical pulse is used only to provide coincidence
with the 545 count (counter preset = 20, 545 20 = 525) in the phase detector circuit. The vertical
ramp is timed by the output of the 525 counter. In standard mode, the NTE849 will maintain the divide
by525 count for six fields of lost or mutilated sync. If the seventh field does not have the correct coin-
cidence, the unit will switch to nonstandard mode. In this mode, the vertical sync is derived from
the integrated vertical pulse on a fieldtofield basis. A noise immunity of 384 lines is provided. In
the absence of sync pulses, the count will be 684 instead of 525 so that rapid vertical capture may
be achieved when sync is restored. Nonsatndard mode still may be selected by removing GND from
Pin8.
The vertical retrace signal is converted to a ramp signal if a capacitor is connected between Pin3 and
GND. The ramps slope corresponds to vertical size and is controlled by changing the input current
to Pin2. The ramp is connected to the inverting input of a diffrence amplifier. The output of this amplifi-
er, connectd to Pin6, is used to drive the vertical output stage. The noninverting input of the differ-
ence amplifier is at Pin5. A voltage derived from yoke current may be applied to this pin for linearity
improvement.
The pulse width of the vertical blanking signal at Pin7 is 608 clocks wide in the synchronous mode,
and is adjustable in width by changing the monostable RC network at Pin10 for the nonsynchronous
mode.
The proportional voltage regulator output at Pin4 is about 43% of the supply voltage at Pin12. The
maximum external load current is 20mA (Peak).
Features:
D Automatic Forced Asynchronous Mode to
Remove Jitter
D Improved Low Voltage StartUp Operation
D Lower ZeroState HorizontalDrive Pulse
Output
D Improved Symmetry for HorizontalDrive
Output
D Improved Automatic Standard Operation
D Noise Detector
D Handles Standard NTSC and NonStandard
Signals
D Automatic Mode Recognition
D Clock Input
D Vertical Ramp (Sawtooth) Generator
D Vertical Amplifier
D Vertical Blanking Generator
D Horizontal Drive Pulse Output
D RatioVoltage Regulator
D Inherent Interlace for NTSC Signals
D VerticalHold Control Eliminated
D Supply Voltage Range: 10.8V to 13.2V
D Rapid PullIn
D CoChannel Sync Lockout for NTSC Signals
D I2L Logic
Absolute Maximum Ratings:
DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Device Dissipation (TA +70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mW
Derate Linearily Above 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7mW/°C
Operating Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55° to +150°C
Lead Temperature (During Soldering, 1/16from case, 10sec max) . . . . . . . . . . . . . . . . . . . . +265°C




 NTE849
Electrical Characteristics: (TA = +25°C, all switches open, test pin 2 & 14 = GND unless
otherwise specified)
Parameter
Test Conditions
Min Max Unit
Amplifier Gain, V6
Horizontal Frequency Divider Ratio, fg ÷ f11
Horizontal Pulse Width, Pin11
S2, S5, S6 Colsed, Note 1 Test pin 1 = 12V,
16 = 1VRMS at 1kHz
S3, S7, S8 Closed, Note 7, Test pin 1 = 14.4V
S3, S7, S8 Closed, Notes 9, 10,
Test pin 1 = 8.4V
0.178 3.16 VRMS
32 32 Ratio
28 34 µs
S3, S7, S8 Closed, Notes 9, 10, 11,
Test pin1 = 14.4V
28 34 µs
Asynchronous NonCoincident Frequency
Divide Ratio, fg ÷ f3
Ramp Charge Pulse Width, Pin3
S3, S7, S8 Closed, Notes 9, 12, 13, 14, 15,
Test pin 1 = 14.4V, 8 = 0.2V, 12 = 1.5V
S3, S7, S8 Closed, Notes 13, 15,
Test pin 1 = 14.4V, 8 = 0.2V, 12 = 1.5V
10944 10944 Ratio
585 585 µs
Asynchronous Coincident Noise Immunity,
HoldOff Frequency Divide Ratio, f8 ÷ f3
Synchronous Divider Ratio, fg ÷ f3
Notes 9, 12, 13, 15, 16, 17, Test pin 1 = 14.4V,
8 = 0.2V
S3, S7, S8 Closed, Notes 9, 13, 15, 18, 19,
Test pin 1 = 14.4V, 8 = 0.2V, 12 = 1.5V
7872 7872
8400 8400
Ratio
Ratio
Ramp Charge Pulse Width, Pin3
S3, S7, S8 Closed, Notes 9, 10, 13, 15, 18, 20, 190 194 Clocks
Test pin 1 = 14.4V, 8 = 0.2V, 12 = 1.5V
Vertical Blanking Pulse Width, Pin7
S3, S7, S8 Closed, Notes 9, 10, 13, 15, 18, 21, 606 610 Clocks
Test pin 1 = 14.4V, 8 = 0.2V, 12 = 1.5V
Mode Recognition Field Count
Frequency Divide Ratio, fg ÷ f3
Synchronous to NonSynchronous
S3, S7, S8 Closed, Notes 9, 13, 14, 15, 18, 22,
Test pin 1 = 12.0V, 8 = 0.2V, 12 = 1.5V
Initial Fields 9 Serrations
8400
8400
Ratio
First Field, 8 Serrations
8400 8400 Ratio
Second Field, 8 Serrations
8400 8400 Ratio
Third Field, 8 Serrations
8400 8400 Ratio
Fourth Field, 8 Serrations
8400 8400 Ratio
Fifth Field, 8 Serrations
8400 8400 Ratio
Sixth Field, 8 Serrations
8400 8400 Ratio
Seventh Field, 8 Serrations
10944 10944 Ratio
Mode Recognition Field Count
Frequency Divide Ratio, fg ÷ f3
NonSynchronous to Synchronous
S3, S7, S8 Closed, Notes 9, 13, 15, 18, 23,
Test pin 1 = 12.0V, 8 = 0.2V
First Field
8384 8384 Ratio
Second Field
8384 8384 Ratio
Third Field
8384 8384 Ratio
Fourth Field
8384 8384 Ratio
Fifth Field
8384 8384 Ratio
Sixth Field
8384 8384 Ratio
Seventh Field
8384 8384 Ratio
Eight Field
8400 8400 Ratio
Ninth Field
8400 8400 Ratio
Fast StandardMode Resynchronization
S3, S7, S8 Closed, Notes 9, 13, 15,
Test pin 1 = 12.0V, 8 = 0.2V




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