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Operational Amplifier. NTE937M Datasheet

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Operational Amplifier. NTE937M Datasheet
















NTE937M Amplifier. Datasheet pdf. Equivalent













Part

NTE937M

Description

JFET Input Operational Amplifier



Feature


NTE937M Integrated Circuit JFET Input Op erational Amplifier Description: The NT E937M is a monolithic JFET input operat ional amplifier in an 8–Lead DIP type package incorporating well–matched, high voltage JFET’s on the same chip with standard bi–polar transistors. T his amplifier features low input bias a nd offset currents, low offset voltage and offset voltage drift, .
Manufacture

NTE Electronics

Datasheet
Download NTE937M Datasheet


NTE Electronics NTE937M

NTE937M; coupled with offset adjust which does no t degrade drift or common–mode reject ion. It is also designed for high slew rate, wide bandwidth, extremely fast se ttling time, low voltage and current no ise and a low 1/f noise corner. Advanta ges: D Replaces Expensive Hybrid and Mo dule FET OP Amps D Rugged JFET’s Allo w Blow–Out Free Handling Compared wit h MOSFET Input Device D .


NTE Electronics NTE937M

Excellent for Low Noise Applications usi ng either High or Low Source Impedance – Very Low 1/f Corner D Offset Adjust does not Degrade Drift or Common–Mod e Rejection as in Most Monolithic Ampli fiers D New Output Stage Allows use of Large Capac .


NTE Electronics NTE937M

.





Part

NTE937M

Description

JFET Input Operational Amplifier



Feature


NTE937M Integrated Circuit JFET Input Op erational Amplifier Description: The NT E937M is a monolithic JFET input operat ional amplifier in an 8–Lead DIP type package incorporating well–matched, high voltage JFET’s on the same chip with standard bi–polar transistors. T his amplifier features low input bias a nd offset currents, low offset voltage and offset voltage drift, .
Manufacture

NTE Electronics

Datasheet
Download NTE937M Datasheet




 NTE937M
NTE937M
Integrated Circuit
JFET Input Operational Amplifier
Description:
The NTE937M is a monolithic JFET input operational amplifier in an 8–Lead DIP type package incor-
porating well–matched, high voltage JFET’s on the same chip with standard bi–polar transistors. This
amplifier features low input bias and offset currents, low offset voltage and offset voltage drift, coupled
with offset adjust which does not degrade drift or common–mode rejection. It is also designed for high
slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f
noise corner.
Advantages:
D Replaces Expensive Hybrid and Module FET OP Amps
D Rugged JFET’s Allow Blow–Out Free Handling Compared with MOSFET Input Device
D Excellent for Low Noise Applications using either High or Low Source Impedance – Very Low
1/f Corner
D Offset Adjust does not Degrade Drift or Common–Mode Rejection as in Most Monolithic Amplifiers
D New Output Stage Allows use of Large Capacitive Loads (10,000pF) without Stability Problems
D Internal Compensation and Large Differential Input Voltage Capability
Applications:
D Precision High Speed Integrators
D Fast D/A and A/D Converters
D High Impedance Buffers
D Wideband, Low Noise, Low Drift Amplifiers
D Logarithmic Amplifiers
D Photocell Amplifiers
D Sample and Hold Circuits
Absolute Maximum Ratings:
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Maximum Power Dissipation (at +25°C, Note 1), Pd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V
Input Voltage Range (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16V
Output Short–Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Maximum Operating Junction Temperature (Note 1), TJmax . . . . . . . . . . . . . . . . . . . . . . . . . . +100°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Thermal Resistance, Junction–to–Ambient (Note 1), RthJC . . . . . . . . . . . . . . . . . . . . . . . . . +155°C/W
Note 1. The maximum power dissipation for this device must be derated at elevated temperatures
and is dictated by TJmax, RthJC, and the ambient temperature, TA. The maximum available
power dissipation at any temperature is Pd = (TJmax – TA)/RthJC or the +25°C Pdmax, which-
ever is less.
Note 2. Unless otherwise specified, the absolute maximum negative input voltage is equal to the
negative power supply voltage.




 NTE937M
DC Electrical Characteristics: (TA = +25C, VS = ±15V unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Supply Current
ICC
5 10 mA
DC Electrical Characteristics: (VS = ±15V, 0° ≤ TA +70°C, THIGH = +70°C unles otherwise
specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Input Offset Voltage
VOS RS = 50, TA = +25°C
Over Temperature
3 10 mV
– – 13 mV
Average TC of Input Offset Voltage
Change in Average TC with VOS
Adjust
VOS/T RS = 50
TC/VOS RS = 50, Note 3
5 µV/°C
0.5 µV/°C
Input Offset Current
Input Bias Current
Input Resistance
Large Signal Voltage Gain
IOS
IB
RIN
AVOL
TJ = +25°C, Note 4
TJ THIGH
TJ = +25°C, Note 4
TJ THIGH
TJ = +25°C
TA = +25°C, VO = ±10V,
RL = 2k
Over Temperature
3 50 pA
– – 2 nA
30 200 pA
– – 8 nA
1012
25 200 V/mV
15 – – V/mV
Output Voltage Swing
VO RL = 10k
RL = 2k
Input CommonMode Voltage Range VCM
±12 ±13
±10 ±12
±10 +15.1
12
V
V
V
CommonMode Rejection Ratio
CMRR
80 100 dB
Supply Voltage Rejection Ratio
PSRR Note 5
80 100 dB
Note 3. The temperature coeficient of the adjust input offset voltage changes only a small amount
(0.5µV/°C typically) for each mV of adjustment from its original unadjusted value. Common
mode rejection and open loop voltage gain are also unaffected by offset adjustment.
Note 4. The input bias currents are junction leakage currents which approximately double for every
10°C increase in the junction temperature, TJ. Due to limited production test time, the input
bias currents measured are correlated to junction temperature. In normal operation the junc-
tion temperature rises above the ambient temperature as a result of internal power dissipa-
tion, Pd. TJ = TA + RthJC Pd where RthJC is the thermal resistance from junction to ambient.
Use of a heat sink is recommended if input bias current is to be kept to a minimum.
Note 5. Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing
simultaneously, in accordance with common practice.




 NTE937M
AC Electrical Characteristics: (TA = +25C, VS = ±15V unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Slew Rate
SR AV = 5
30 50 V/µs
Gain Bandwidth Product
GBW
20 MHz
Settling Time to 0.01%
Equivalent Input Noise Voltage
ts Note 6
1.5
µs
eN RS = 100f = 100Hz
15 nV/Hz
f = 1000Hz 12 nV/Hz
Equivalent Input Current Noise
iN f = 100Hz
f = 1000Hz
0.01 pA/Hz
0.01 pA/Hz
Input Capacitance
CIN
3 pF
Note 6. AV = 5, the feedback resistor from output to input is 2kand the output step is 10V.
Pin Connection Diagram
Offset Null 1
Inverting Input 2
NonInverting Input 3
VEE 4
8 N.C.
7 VCC
6 Output
5 Offset Null
85
.260 (6.6)
14
.390 (9.9)
Max
.155
(3.93)
.300
(7.62)
.100 (2.54)
.300 (7.62)
.145 (3.68)




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