NDP4050 / NDB4050
N-Channel Enhancement Mode Field Effect Transistor
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high
density process has been especially tailored to minimize
on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls, and
other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are
15A, 50V. RDS(ON) = 0.10Ω @ VGS=10V.
Critical DC electrical parameters specified at elevated
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low RDS(ON).
TO-220 and TO-263 (D2PAK) package for both through hole
and surface mount applications.
Absolute Maximum Ratings
TC = 25°C unless otherwise noted
VDSS Drain-Source Voltage
Drain-Gate Voltage (RGS < 1 MΩ)
VGSS Gate-Source Voltage - Continuous
- Nonrepetitive (tP < 50 µs)
ID Drain Current - Continuous
PD Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
-65 to 175
© 1997 Fairchild Semiconductor Corporation
NDP4050 Rev. B