|
|
Monitor Chip. DS1231S Datasheet |
|
|
|
DS1231/S
DS1231/S
Power Monitor Chip
FEATURES
• Warns processor of an impending power failure
• Provides time for an orderly shutdown
• Prevents processor from destroying nonvolatile
memory during power transients
• Automatically restarts processor after power is
restored
• Suitable for linear or switching power supplies
• Adjusts to hold time of the power supply
• Supplies necessary signals for processor interface
• Accurate 5% or 10% VCC monitoring
• Replaces power-up reset circuitry
• No external capacitors required
• Optional 16-pin SOIC surface mount package
DESCRIPTION
The DS1231 Power Monitor Chip uses a precise tem-
perature-compensated reference circuit which provides
an orderly shutdown and an automatic restart of a pro-
cessor-based system. A signal warning of an impending
power failure is generated well before regulated DC
voltages go out of specification by monitoring high volt-
age inputs to the power supply regulators. If line isola-
tion is required a UL-approved opto-isolator can be di-
rectly interfaced to the DS1231. The time for processor
PIN ASSIGNMENT
IN
MODE
TOL
GND
1
2
3
4
8 VCC
7 NMI
6 RST
5 RST
DS1231 8–Pin DIP
(300 MIL)
See Mech. Drawings
Section
NC 1 16 NC
IN 2 15 VCC
NC 3 14 NC
MODE 4 13 NMI
NC 5 12 NC
TOL 6 11 RST
NC 7 10 NC
GND
8
9 RST
DS1231S 16–Pin SOIC
(300 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN – Input
MODE
– Selects input pin characteristics
TOL
GND
– Selects 5% or 10% VCC detect
– Ground
RST
– Reset (Active High)
RST
– Reset (Active Low, open drain)
NMI – Non–Maskable Interrupt
VCC – +5V Supply
NC – No Connections
shutdown is directly proportional to the available
hold-up time of the power supply. Just before the
hold-up time is exhausted, the Power Monitor uncondi-
tionally halts the processor to prevent spurious cycles
by enabling Reset as VCC falls below a selectable 5 or
10 percent threshold. When power returns, the proces-
sor is held inactive until well after power conditions have
stabilized, safeguarding any nonvolatile memory in the
system from inadvertent data changes.
022698 1/9
|
DS1231/S
OPERATION
The DS1231 Power Monitor detects out-of-tolerance
power supply conditions and warns a processor-based
system of impending power failure. The main elements
of the DS1231 are illustrated in Figure 1. As shown, the
DS1231 actually has two comparators, one for monitor-
ing the input (Pin 1) and one for monitoring VCC (Pin 8).
The VCC comparator outputs the signals RST (Pin 5)
and RST (Pin 6) when VCC falls below a preset trip level
as defined by TOL (Pin 3).
When TOL is connected to ground, the RST and RST
signals will become active as VCC goes below 4.75
volts. When TOL is connected to VCC, the RST and RST
signals become active as VCC goes below 4.5 volts. The
RST and RST signals are excellent control signals for a
microprocessor, as processing is stopped at the last
possible moments of valid VCC. On power-up, RST and
RST are kept active for a minimum of 150 ms to allow the
power supply to stabilize (see Figure 2).
The comparator monitoring the input pin produces the
NMI signal (Pin 7) when the input threshold voltage
(VTP) falls to a level as determined by Mode (Pin 2).
When the Mode pin is connected to VCC, detection oc-
curs at VTP-. In this mode Pin 1 is an extremely high im-
pedance input allowing for a simple resistor voltage di-
vider network to interface with high voltage signals.
When the Mode pin is connected to ground, detection
occurs at VTP+. In this mode Pin 1 sources 30 µA of cur-
rent allowing for connection to switched inputs, such as
a UL-approved opto-isolator. The flexibility of the input
pin allows for detection of power loss at the earliest point
in a power supply system, maximizing the amount of
time allotted between NMI and RST. On power-up, NMI
is released as soon as the input threshold voltage (VTP)
is achieved and VCC is within nominal limits. In both
modes of operation the input pin has hysteresis for
noise immunity (Figure 3).
APPLICATION – MODE PIN
CONNECTED TO VCC
When the Mode pin is connected to VCC, pin 1 is a high
impedance input. The voltage sense point and the level
of voltage at the sense point are dependent upon the
application (Figure 4). The sense point may be devel-
oped from the AC power line by rectifying and filtering
the AC. Alternatively, a DC voltage level may be se-
lected which is closer to the AC power input than the
regulated +5-volt supply, so that ample time is provided
for warning before regulation is lost.
Proper operation of the DS1231 requires a maximum
voltage of 5 volts at the input (Pin 1), which must be
derived from the maximum voltage at the sense point.
This is accomplished with a simple voltage divider net-
work of R1 and R2. Since the IN trip point VTP- is 2.3
volts (using the -20 device), and the maximum allowable
voltage on pin 1 is 5 volts, the dynamic range of voltage
at the sense point is set by the ratio of 2.3/5.0=.46 min.
This ratio determines the maximum deviation between
the maximum voltage at the sense point and the actual
voltage which will generate NMI.
Having established the desired ratio, and confirming
that the ratio is greater than .46 and less than 1, the
proper values for R1 and R2 can be determined by the
equation as shown in Figure 4. A simple approach to
solving this equation is to select a value for R2 which is
high enough impedance to keep power consumption
low, and solve for R1. Figure 5 illustrates how the
DS1231 can be interfaced to the AC power line when
the mode pin is connected to VCC.
022698 2/9
|
POWER MONITOR BLOCK DIAGRAM Figure 1
IN
1
30mA
GND
4
NMI
MODE
SELECTION
VCC
8
TOL
3
VCC
TOLERANCE
BIAS
DIGITAL
SAMPLER
DIGITAL
DELAY
DS1231/S
MODE
2
NMI
7
RST
6
RST
5
T.C. REFERENCE
POWER-UP RESET Figure 2
DS1231
IN VCC
MODE
NMI
TOL
RST
GND
RST
+5V
NC
(-5% VCC THRESHOLD)
MICROPROCESSOR
RST
8051
µP
022698 3/9
|
| @ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |