Cordless Telephones. MC145167 Datasheet

MC145167 Telephones. Datasheet pdf. Equivalent

Part MC145167
Description Dual PLLs for 46/49 MHz Cordless Telephones
Feature MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC145166/D Dual PLLs for 46/49 MHz Co.
Manufacture Motorola
Datasheet
Download MC145167 Datasheet



MC145167
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145166/D
Dual PLLs for 46/49 MHz
Cordless Telephones
CMOS
These devices are dual phase–locked loop (PLL) frequency synthesizers in–
tended for use primarily in 46/49 MHz cordless phones with up to 10 channels.
These parts contain two mask–programmable counter ROMs for receive and
transmit loops with two independent phase detect circuits. A common reference
oscillator and reference divider are shared by the receive and transmit circuits.
Frequency selection is accomplished via a 4–bit parallel input for the
MC145166. The MC145167 utilizes a serial interface.
Other features include a lock detect circuit for the transmit loop, illegal code
default, and a 5 kHz tone output.
Synthesizes Up to Ten Channel Pairs
Maximum Operating Frequency: 60 MHz @ Vin = 200 mV p–p
Operating Temperature Range: – 40 to + 75°C
Operating Voltage Range: 2.5 to 5.5 V
On–Chip Oscillator Circuit Supports External Crystal
Lock Detect Signal
Operating Power Consumption: 3.0 mA @ 3.0 V
Standby Mode for Power Savings: 1.5 mA @ 3.0 V
Also See MC145162
MC145166
MC145167
16
1
P SUFFIX
PLASTIC DIP
CASE 648
16
1
DW SUFFIX
SOG PACKAGE
CASE 751G
ORDERING INFORMATION
MC145166P Plastic DIP
MC145166DW SOG Package
MC145167P Plastic DIP
MC145167DW SOG Package
PIN ASSIGNMENTS
MC145166P
MC145166DW
OSCout
MODE
SB
5k
1
2
3
4
16 OSCin
15 VDD
14 fin1
13 PD1
D0 5
D1 6
12 VSS
11 PD2
D2 7
10 LD
D3 8
9 fin2
MC145167P
MC145167DW
OSCout
MODE
SB
5k
DATA
CLK
1
2
3
4
5
6
16 OSCin
15 VDD
14 fin1
13 PD1
12 VSS
11 PD2
NC 7
10 LD
ENB 8
9 fin2
NC = NO CONNECTION
REV 2
1/98 TN98011400
©MOMoTtoOroRla,OInLc.A1998
MC145166MC145167
1



MC145167
fin1
SB *
fin2
BLOCK DIAGRAM
13–BIT DIVIDE–BY–N
RECEIVE COUNTER
fv = 5 kHz
fr
PHASE
DET 1
13
RECEIVE
ROM
TRANSMIT
ROM
14
LOCK
DET
14–BIT
DIVIDE–BY–N
TRANSMIT
COUNTER
fv
PHASE
DET 2
PD1
VDD
LD
PD2
OSCin
OSCout
5k
VSS
* On–chip pull–down.
REFERENCE
COUNTER
DIVIDE–BY–2048
5 kHz
fr
DECODE
LOGIC
MODE
*
D0
* MC145166
D1 ONLY
*
D2
*
D3
4–BIT LATCH
ENB
4–BIT S/R
CLK
DATA
MC145167 ONLY
MC145166MC145167
2
MOTOROLA





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