MODE. IC41C44002A Datasheet

IC41C44002A Datasheet PDF


Part

IC41C44002A

Description

4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Manufacture

ICSI

Page 20 Pages
Datasheet
Download IC41C44002A Datasheet


IC41C44002A Datasheet
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
Document Title
4Mx4 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
0A
History
Initial Draft
Draft Date
Remark
September 4,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
1

IC41C44002A Datasheet
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Self Refresh 2048 cycles for S version
• Low power for L version.
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IS41C44002A
2K 5V ± 10%
IS41C44002AS(L)
2K
5V ± 10%
IS41LV44002A
2K 3.3V ± 10%
IS41LV44002AS(L) 2K
3.3V ± 10%
PIN CONFIGURATION
24 Pin SOJ, TSOP-2
VCC
I/O0
I/O1
WE
RAS
NC
1
2
3
4
5
6
24 GND
23 I/O3
22 I/O2
21 CAS
20 OE
19 A9
A10
A0
A1
A2
A3
VCC
7
8
9
10
11
12
18 A8
17 A7
16 A6
15 A5
14 A4
13 GND
DESCRIPTION
The ICSI 44002 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These devices
offer an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 2,048 random accesses within a single
row with access cycle time as short as 20 ns per 4-bit word.
These features make the 44002 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 44002 Series is packaged in a 24-pin 300mil SOJ and a 24
pin TSOP-2
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
-50 -60 Unit
50 60 ns
13 15 ns
25 30 ns
20 25 ns
84 104 ns
PIN DESCRIPTIONS
A0-A10
I/O0-3
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs (2K Refresh)
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
DR026-0A 09/04/2001


Features Datasheet pdf IC41C44002A/IC41C44002AS(L) IC41LV44002A /IC41LV44002AS(L) Document Title 4Mx4 b it Dynamic RAM with EDO Page Mode Revi sion History Revision No 0A History In itial Draft Draft Date September 4,200 1 Remark The attached datasheets are provided by ICSI. Integrated Circuit So lution Inc reserve the right to change the specifications and products. ICSI w ill answer to your questions about devi ce. If you have any questions, please c ontact the ICSI offices. Integrated Ci rcuit Solution Inc. DR026-0A 09/04/2001 1 IC41C44002A/IC41C44002AS(L) IC41LV 44002A/IC41LV44002AS(L) 4M x 4 (16-MBI T) DYNAMIC RAM WITH EDO PAGE MODE FEATU RES • Extended Data-Out (EDO) Page Mo de access cycle • TTL compatible inpu ts and outputs • Refresh Interval: -- 2,048 cycles/32 ms • Refresh Mode: R AS-Only, CAS-before-RAS (CBR), and Hidd en • JEDEC standard pinout • Single power supply: 5V ± 10% or 3.3V ± 10% • Self Refresh 2048 cycles for S ver sion • Low power for L version. DESCRIPTION The ICSI 44002 Series is a 4,194,3.
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