KM48S8030C
Revision History
Revision 0.0 (Oct., 1998)
PC133 first published.
Preliminary PC133 CMOS SDRAM
REV. 0 Oct. '98
KM48S8030C
2M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst lengt...
