64K EEPROM. 28C64A Datasheet

28C64A EEPROM. Datasheet pdf. Equivalent

Part 28C64A
Description High Speed CMOS 64K EEPROM
Feature Turbo IC, Inc. 28C64A HIGH SPEED CMOS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM .
Manufacture Turbo IC
Datasheet
Download 28C64A Datasheet

28C64A 64K (8K x 8) CMOS EEPROM FEATURES • Fast Read Access 28C64A Datasheet
28C64A 64K (8K x 8) CMOS EEPROM FEATURES • Fast Read Access 28C64A Datasheet
Turbo IC, Inc. 28C64A HIGH SPEED CMOS 64K ELECTRICALLY ERAS 28C64A Datasheet
28C64A 64K (8K x 8) CMOS EEPROM FEATURES • Fast Read Access 28C64A Datasheet
Turbo IC, Inc. 28C64A HIGH SPEED CMOS 64K ELECTRICALLY ERAS 28C64A Datasheet
Recommendation Recommendation Datasheet 28C64A Datasheet




28C64A
Turbo IC, Inc.
28C64A
HIGH SPEED CMOS
64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
8K X 8 BIT EEPROM
FEATURES:
• 120 ns Access Time
• Automatic Page Write Operation
Internal Control Timer
Internal Data and Address Latches for 64 Bytes
• Fast Write Cycle Times
Byte or Page Write Cycles: 10 ms
Time to Rewrite Complete Memory: 1.25 sec
Typical Byte Write Cycle Time: 160 µsec
• Software Data Protection
• Low Power Dissipation
50 mA Active Current
200 µA CMOS Standby Current
• Direct Microprocessor End of Write Detection
Data Polling
• High Reliability CMOS Technology with Self Redundant
EEPROM Cell
Endurance: 100,000 Cycles
Data Retention: 10 Years
• TTL and CMOS Compatible Inputs and Outputs
• Single 5 V ± 10% Power Supply for Read and
Programming l Operations
• JEDEC Approved Byte-Write Pinout
DESCRIPTION:
The Turbo IC 28C64A is a 8K X 8 EEPROM fabricated with
Turbo’s proprietary, high reliability, high performance CMOS
technology. The 64K bits of memory are organized as 8K
by 8 bits.The device offers access time of 120 ns with power
dissipation below 250 mW.
The 28C64A has a 64-bytes page write operation enabling
the entire memory to be typically written in less than 1.25
seconds. During a write cycle, the address and 1 to 64 bytes
of data are internally latched, freeing the address and data
bus for other microprocessor operations.The programming
process is automatically controlled by the device using an
internal control timer. Data polling on one or all I/O can be
used to detect the end of a programming cycle. In addition,
the 28C64A includes an user-optional software data write
mode offering additional protection against unwanted (false)
write. The device utilizes an error protected self redundant
cell for extended data retention and endurance.
A7 NC VCC NC
A12 NC WE
A6 5 4 3 2 1 32 313029 A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13 21
14 15 16 17 18 19 20
I/O6
I/O1 GND I/O3 I/O5
I/O2 NC I/O4
32 pins PLCC
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
28 VCC
27 WE
26 NC
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
28 pins PDIP
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
OE 1
28 VCC A11
2
A9 3
27 WE A8
4
NC 5
26 NC WE
6
VCC 7
25 A8 NC
8
A12 9
24 A9
A7
10
A6 11
23 A11 A5
12
A4 13
22 OE A3
14
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
28 pins SOIC (SOG)
28 pins TSOP
28 A10
27 CE
26 I/O7
25 I/O6
24 I/O5
23 I/O4
22 I/O3
21 GND
20 I/O2
19 I/O1
18 I/O0
17 A0
16 A1
15 A2
PIN DESCRIPTION
ADDRESSES (A0 - A12)
The Addresses are used to select an 8 bits
memory location during a write or read opera-
tion.
OUTPUT ENABLE (OE)
The Output Enable input activates the output buff-
ers during the read operations.
CHIP ENABLES (CE)
The Chip Enable input must be low to enable all
read/write operation on the device. By setting CE
high, the device is disabled and the power con-
sumption is extremely low with the standby cur-
rent below 200 µA.
WRITE ENABLE (WE)
The Write Enable input initiates the writing of data
into the memory.
DATA INPUT/OUTPUT (I/O0-I/O7)
Data Input/Output pins are used to read data out
of the memory or to write Data into the memory.



28C64A
Turbo IC, Inc.
28C64A
DEVICE OPERATION
READ:
The 28C64A is accessed like a static RAM. Read operations are initiated
by both CE and OE going low and terminated by either CE or OE return-
ing high. The outputs are at the high impedance state whenever CE or
OE returns high. The two line control architecture gives designers flex-
ibility in preventing bus contention.
WRITE:
A write cycle is initiated when CE and WE are low and OE is high. The
address is latched internally on the falling edge of CE or WE whichever
occurs last. The data is latched by the rising edge of CE or WE whichever
occurs first. Once a byte write cycle has been started, the internal timer
automatically generates the write sequence to the completion of the write
operation.
PAGE WRITE OPERATION:
The page write operation of 28C64A allows one to 64 bytes of data to be
serially loaded into the device and then simultaneously written into memory
during the internally generated write cycle. After the first byte has been
loaded, successive bytes of data may be loaded until the full page of 64
bytes is loaded. Each new byte to be written must be loaded within 200
µs of the previously loaded byte. The page address defined by the ad-
dresses A6-A12 is latched by the first CE or WE falling edge which ini-
tiates a writing cycle and they will stay latched until the completion of the
page write. Any changes in the page addresses during the load-write
cycle will not affect the initially latched page addresses. Addresses A0 -
A5 are used to define which bytes will be loaded and written within the 64
bytes page. The bytes may be loaded in any order that is convenient to
the user. The content of a loaded byte may be altered at any time during
the loading cycle if the maximum allowed byte-load time (200 µs) is not
exceeded. Only loaded bytes within the page will be written; no rewriting
will occur to the non-selected bytes in the page.
DATA POLLING:
The 28C64A features DATA POLLING to indicate the completion of a
write cycle to the host system. During a byte or page write cycle, an
attempted read of the last byte loaded into the page will result in the
complement of the loaded byte on all outputs I/O0 - I/O7 (i.e. loaded data
01010110, read data 10101001). Data Polling feature may be used by an
attempted read on one or more outputs (whatever is convenient for the
system developer). Once the write cycle has been completed, true data
is valid on all outputs and the next cycle may be started.
DATA PROTECTION:
The 28C64A has three hardware features to protect the written content
of the memory against inadvertent writes :
a.) Vcc threshold detector: If Vcc is below 2.5 V, the write capa-
bilities of the chip is inhibited for whatever input conditions.
b.) Noise protection: A WE, OE, or CE pulse less than 10 ns in
width is not able to initiate a write cycle.
c.) Write inhibit: Holding OE at low, or CE at high, or WE at high
inhibits the write cycle.
SOFTWARE WRITE PROTECTION:
The 28C64A offers a software controlled data write protection feature. The
device is delivered to the user with the software data write protection DIS-
ABLED; i.e. the device will go to the data write operation as long as Vcc
exceeds 2.5 V and CE, WE, and OE inputs are set at write mode levels.
The 28C64A can be automatically protected against an accidental write
operation during power-up or power-down without any external circuitry by
enabling the software data write protection features. This features is en-
abled after the first write cycle which includes the software algorithm. After
this operation is done, the data write function of the device may be per-
formed only if every page write cycle is preceded by the software algo-
rithm. The device will maintain its software protect feature for the rest of its
life unless that the software algorithm for disabling the protection is imple-
mented.
SOFTWARE ALGORITHM:
The 28C64A has an internal register for the software algorithm which en-
ables the memory to provide the user with additional features:
a.) Software Write Protect Enable
A sequence of three dummy data writes to the memory will activate
internal EEPROM fuses during the first page write cycle. These EE-
PROM fuses will reject any write attempts of new pages of data
unless the three dummy data writes are repeated at the beginning of
any page writes. The timing for the dummy data and addresses must
be the same as for a normal write operation. A violation of the three
steps write protect sequence in data or address timing and content
will abort the procedure and reset the device to the starting point
condition.
Note: After the three dummy data writes, at least one page load/
write cycle must be performed. If no additional page data is added
to the three dummy data writes, the software write protect will
not be enabled until the next write, which will not be protected.
Table 1 shows the required procedure for enabling the software write
protect:
Step
1
2
3
4-67
Mode
Page Write
Page Write
Page Write
Page Write
Address A12-A0
1555 Hex
0AAA Hex
1555 Hex
Address
Data I/O 7-0
AA Hex
55 Hex
A0 Hex
Data
b.) Software Write Protect Disable
The software algorithm of 28C64A includes a six steps sequence of
dummy data writing to disable the software write protect feature de-
scribed in a.). The six steps write sequence shown in Table 2 must
be performed at the beginning of a page write cycle. A violation of
the six steps write sequence in data or address timing and content
will abort the procedure and reset the chip to the starting point con-
dition. After a page write cycle including the six steps write sequence
has been performed, the 28C64A does not require the use of three
dummy data writes described in a.) for the following page write cycle.
The device is at the software write protect disabled state.
Note: After the six dummy data writes, at least one page load/
write cycle must be performed. If no additional page data is added
to the six dummy data writes, the software write protect disable
will not be activated. Table 2 shows the required procedure for dis-
abling the software write protect:
step
1
2
3
4
5
6
7-70
Mode
Page Write
Page Write
Page Write
Page Write
Page Write
Page Write
Page Write
Address A12-A0
1555 Hex
0AAA Hex
1555 Hex
1555 Hex
0AAA Hex
1555 Hex
Address
Data I/O 7-0
AA Hex
55 Hex
80 Hex
AA Hex
55 Hex
20 Hex
Data
c.) Software Chip Clear
The software algorithm of 28C64A includes a sequence of six steps
dummy data writing to perform a chip clear operation. Table 3 shows
the six steps write sequence to perform the software chip clear op-
eration:
Step
1
2
3
4
5
6
Mode
Page Write
Page Write
Page Write
Page Write
Page Write
Page Write
Address A12-A0
1555 Hex
0AAA Hex
1555 Hex
1555 Hex
0AAA Hex
1555 Hex
Data I/O 7-0
AA Hex
55 Hex
80 Hex
AA Hex
55 Hex
10 Hex
At the end of the six steps write sequence shown in Table 3, the
device automatically activates its internal timer to control the chip





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