Digital Converter. 7809LP Datasheet

7809LP Converter. Datasheet pdf. Equivalent

Part 7809LP
Description 16-Bit Latchup Protected Analog to Digital Converter
Feature 16-Bit Latchup Protected Analog to Digital Converter 7809LP R/C CS POWER DOWN Successive Approx.
Manufacture Maxwell Technologies
Datasheet
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16-Bit Latchup Protected Analog to Digital Converter 7809LP 7809LP Datasheet
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7809LP
7809LP
16-Bit Latchup Protected
Analog to Digital Converter
20 k
R1IN
10 k
R2IN
5 k
R3IN
20 k
CAP
REF
R/C
Buffer
CS POWER DOWN
Successive Approximation Register and Control Logic
CDAC
Clock
Comparator
Serial Data
Out
BUSY
Data
Clock
Serial
Data
Internal
+2.5V Ref.
4 k
Logic Diagram
FEATURES:
• RAD-PAK® radiation-hardened against natural
• space radiation
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Latch-up Protection Technology (LPTTM)
• SEL converted into a reset
- Rate based on cross section and mission
• Same footprint as ADS7809
• Package: 24 pin RAD-PAK flat package
• 100 kHz min sampling rate
• ±10 V and 0 V to 5 V input range
• DNL: 15-bits “No Missing Codes”
• 83 dB min SINAD with 20 kHz input
• Single +5 V supply operation
• Utilizes internal or external reference
• Serial output
• Power dissipation: 132 mW max
DESCRIPTION:
Maxwell Technologies’ 7809LP high-speed 16-bit analog to
digital converter features a greater than 100 kilorad (Si) total
dose tolerance depending upon space mission. Using Max-
well’s radiation-hardened RAD-PAK® packaging technology, the
7809LP has the same footprint as ADS7809 and is latchup
protected by Maxwell Technologies’ Latchup Protection Tech-
nology (LPTTM). It is a 24 pin, 16-bit sampling analog-to-digital
converter using state-of-the-art CMOS structures. The
7809LP contains a 16-bit capacitor based SAR A/D with S/H,
reference, clock, interface for microprocessor use, and serial
output drivers. The 7809LP is specified at a 100kHz sampling
rate, and guaranteed over the full temperature range. Laser-
trimmed scaling resistors provide various input ranges include
±10 V and 0 to 5 V, while the innovative design allows opera-
tion from a single +5 V supply, with power dissipation of under
132 mW.
Maxwell Technologies' patented RAD-PAK® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK® provides greater than 50
krad (Si) radiation dose tolerance. This product is available
with screening up to Maxwell Technologies self-defined Class
K.
01.11.05 Rev 7
(858) 503-3300- Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice 1
©2005 Maxwell Technologies
All rights reserved.



7809LP
16-Bit Latchup Protected Analog to Digital Converter 7809LP
TABLE 1. 7809LP PIN DESCRIPTION
PIN SYMBOL
DESCRIPTION
1 R1IN Analog Input.
2 AGND1 Analog Ground. Used internally as ground reference point.
3 R2IN Analog Input.
4 R3IN Analog Input.
5 CAP Reference Buffer Capacitor. 2.2 µ F tantalum to ground.
6 REF Reference Input/Output. 2.2 µ F tantalum capacitor to ground.
7 AGND2 Analog Ground.
8 SB/BTC Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be
output in a Straight Binary format. If LOW, data will be output in a Binary Two’s Complement
format.
9 EXT/INT Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized
to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the
data from the previous conversion, along with 16 clock pulses output on DATACLK.
10 DGND Digital Ground.
11 LPBIT Built In test function of the latchup protection. Drive LOW during normal operation.
12 LPSTATUS Latchup Protection Status Output. LPSTATUS when HIGH indicates latchup protection is
active and output data is invalid.
13 VANA Analog Supply Input. Nominally 5V.
14 VDIG Digital Supply Input. Nominally 5V.
15 SYNC Sync Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on
CS with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK.
16 DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized
to this clock. If EXT/INT is LOW, DATACLK will transmit 16 pulses after each conversion, and
then remain LOW between conversions.
17 DATA Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the
level of SB/BTC. In the external clock mode, after 16-bits of data, the 7809LOPO will output the
level input of TAG as long as CS is LOW and R/C is HIGH. If EXT/INT is LOW, data will be valid
on both the rising and falling edges of DATACLK, and between conversions DATA will stay at
the level of the TAG input when the conversion was started.
18 TAG Tag input for use in external clock mode. If EXT/INT is HIGH, the digital data input on TAG will
be output on DATA with a delay of 16 DATACLK pulses as long as CS is LOW and R/C is
HIGH.
19 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the
hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission
of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with
CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the
transmission of data from the previous conversion.
20 CS Chip Select. Internally OR’ed with R/C.
01.11.05 Rev 7
All data sheets are subject to change without notice 2
©2005 Maxwell Technologies
All rights reserved.





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