74LS107 Flip-Flops Datasheet

74LS107 Datasheet PDF, Equivalent


Part Number

74LS107

Description

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

Manufacture

ETC

Total Page 6 Pages
PDF Download
Download 74LS107 Datasheet PDF


74LS107
June 1989
DM54LS107A DM74LS107A Dual Negative-Edge-
Triggered Master-Slave J-K Flip-Flops with
Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse The data on the J
and K inputs may change while the clock is high or low
without affecting the outputs as long as setup and hold
times are not violated A low logic level on the clear input
will reset the outputs regardless of the logic levels of the
other inputs
Connection Diagram
www.DataSheet4U.com
Dual-In-Line Package
TL F 6367 – 1
Order Number DM54LS107AJ DM54LS107AW DM74LS107AM or DM74LS107AN
See NS Package Number J14A M14A N14A or W14B
Function Table
Inputs
Outputs
CLR CLK J K
Q
Q
L
X
XX
L
H
vH
L L Q0
Q0
H v HL H L
H v LH L H
H v HH
Toggle
H
H
X X Q0
Q0
H e High Logic Level
X e Either Low or High Logic Level
L e Low Logic Level
v e Negative going edge of pulse
Q0 e The output logic level before the indicated input conditions were established
Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse
C1995 National Semiconductor Corporation TL F 6367
RRD-B30M105 Printed in U S A

74LS107
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
b55 C to a125 C
DM74LS
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM54LS107A
Min Nom Max
VCC Supply Voltage
45 5 55
VIH High Level Input Voltage
2
VIL Low Level Input Voltage
07
IOH High Level Output Current
www.DataShIOeLet4U.comLow Level Output Current
b0 4
4
fCLK
Clock Frequency (Note 2)
0
30
fCLK
Clock Frequency (Note 3)
0
25
tW
Pulse Width
Clock High
20
(Note 2)
Clear Low
25
tW
Pulse Width
Clock High
25
(Note 3)
Clear Low
30
tSU Setup Time (Notes 1 2)
20v
tSU Setup Time (Notes 1 3)
25v
tH Hold Time (Notes 1 2)
0v
tH Hold Time (Notes 1 3)
5v
TA
Free Air Operating Temperature
b55
vNote 1 The symbol ( ) indicates the falling edge of the clock pulse is used for reference
Note 2 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 3 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V
125
DM74LS107A
Min Nom Max
4 75 5 5 25
2
08
b0 4
8
0 30
0 25
20
25
25
30
20v
25v
0v
5v
0 70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
ns
ns
C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min Typ
Max Units
(Note 1)
VI
VOH
Input Clamp Voltage
VCC e Min II e b18 mA
b1 5
V
High Level Output
Voltage
VCC e Min IOH e Max
VIL e Max VIH e Min
DM54
DM74
25
27
34
34
V
VOL
Low Level Output
VCC e Min IOL e Max
DM54
Voltage
VIL e Max VIH e Min
DM74
0 25 0 4
0 35 0 5 V
IOL e 4mA VCC eMin
DM74
II
Input Current Max
VCC e Max VI e 7V
JK
Input Voltage
Clear
0 25 0 4
01
0 3 mA
Clock
04
2


Features DM54LS107A DM74LS107A Dual Negative-Edge -Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs J une 1989 DM54LS107A DM74LS107A Dual Ne gative-EdgeTriggered Master-Slave J-K F lip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge -triggered J-K flip-flops with compleme ntary outputs The J and K data is proce ssed by the flip-flops on the falling e dge of the clock pulse The clock trigge ring occurs at a voltage level and is n ot directly related to the transition t ime of the negative going edge of the c lock pulse The data on the J and K inpu ts may change while the clock is high o r low without affecting the outputs as long as setup and hold times are not vi olated A low logic level on the clear i nput will reset the outputs regardless of the logic levels of the other inputs Connection Diagram Dual-In-Line Packa ge www.DataSheet4U.com TL F 6367 – 1 Order Number DM54LS107AJ DM54LS107AW DM74LS107AM or DM74LS107A.
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