ADD8502 Generator Datasheet

ADD8502 Datasheet PDF, Equivalent


Part Number

ADD8502

Description

Integrated LCD Grayscale Generator

Manufacture

Analog Devices

Total Page 16 Pages
PDF Download
Download ADD8502 Datasheet PDF


ADD8502
a
Integrated LCD
Grayscale Generator
ADD8502
FEATURES
Two Mask Programmable Sets of Five Reference Levels
Dual 10-Bit DACs for Flicker Offset and Range Adjustment
Integrated VCOM Switching
Single-Supply Operation: 5.0 V
Low Supply Current: 300 A
Global Power Save Mode: 1 A Max
Fast Settling Time for Load Change: 20 s
Stable with 20 nF/100 Loads
CMOS/TTL Input Levels
APPLICATIONS
Color TFT Cell Phones
Color TFT PDAs
GENERAL DESCRIPTION
The ADD8502 is an integrated, high accuracy, programmable
grayscale generator. Two sets of five output reference voltages
are mask programmed to 0.2% resolution. The outputs switch
between the two sets of five levels. The reference levels are selected
from a 512 tap resistor network using a via mask.
ADD8502 includes two serially addressable, 10-bit digital-to-
analog converters (DACs) and five fast, low current buffers.
The dual DACs set the endpoint voltages applied to the resistor
network to adjust for flicker and range. The two power save modes
can reduce the total current to less than 1 µA and feature fast
recovery time from Shutdown/Sleep Mode. The ADD8502
accepts CMOS or TTL inputs for all controls, including the
common drive circuit levels.
ADD8502 operates over the industrial temperature range from
–40°C to +85°C and is available in a space-saving 24-lead
4 mm ϫ 4 mm frame chip scale package.
FUNCTIONAL BLOCK DIAGRAM
REV2
VDD
VREF+
VDD/2
10-BIT
DAC A
VREF–
VL
VP0
VN0
R
R VP0
R
VN4
A0
A1
SCK
DIN
CS-LD
DIGITAL
CORE
POWER
SAVE
LOGIC
PSK
GS1
GS2
VDD/2
VREF+
10-BIT
DAC B
VREF–
MUX
VP4
VN4
R
VP4
R
VN0
R
R
VDD
A2
A3
A4
VCOM
LOGIC
VDD
GND
V0
V1
V2
V3
V4
COM
COM_M
REV1 CM CV4
sheet4u.comREV. 0
taInformation furnished by Analog Devices is believed to be accurate and
areliable. However, no responsibility is assumed by Analog Devices for its
.duse, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or
wwwotherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

ADD8502
ADD8502–SPECIFICATIONS (@ VDD = 5.0 V, ؊40؇C TA ؉85؇C, unless otherwise noted.)
Parameter
Symbol Conditions
Min Typ Max
Unit
SYSTEM ACCURACY
VOUT Error
Swing Error1
Mean Error2
Mean Error between Adjacent Channels3
Mean Error between V0 and V44
(VPn – VNn) – (VPi – VNi)
(VPn+ VNn)/2 – (VPi + VNi)/2)
3 20
1 17
3 21
3 21
3 25
mV
mV
mV
mV
mV
DAC ACCURACY
Resolution
Differential Nonlinearity
Integral Nonlinearity5
Offset Error
Gain Error
OUTPUT CHARACTERISTICS
Output Current
Short Circuit Current
Output Leakage Current in High-Z Mode
Slew Rate
Settling Time to 1%
Slew Rate5
Settling Time to 1%5
Phase Margin
VCOM SWITCHES ACTIVE IMPEDANCE
COM to VDD
COM to GND
COM to COM_M
COM to V4
DNL
INL
IOUT
ISC
ILEAKAGE
SR
tS
SR
tS
φo
(VDD – 1 V)
Short to Ground
High-Z Mode
RL = 100 k
V0 to V4 Step Size
LD =100 Series 16 nF
V0 to V4 Step Size
Z See Table IV
Z
Z I = 20 mA
Z
10
± 0.25
± 0.5
± 0.4
± 0.15
25
60
0.01 1.0
1.25
8 12
0.7
8 12
67
25 50
25 50
25 50
25 50
Bits
LSB
LSB
% of FSR
% of FSR
mA
mA
µA
V/µs
µs
V/µs
µs
Degrees
MASK PROGRAMMABLE
RESISTOR CHAIN
Resistor Matching
RMATCH Any Two Segments between
512 Resistor String
1
%
POWER SUPPLY
Supply Voltage
Supply Current
Shutdown Supply Current
Sleep Supply Current
Shutdown Recovery Time
Sleep Recovery Time
VDD
ISY
ISY-GLB
ISY-GS1-3
VDD = 5 V; No Load
Full Shutdown Mode
Mid 3 Buffers Shutdown
Global PD to 1%
V1–V3 Off to 1%
4.5 5
5.5
190 270 400
0.2 1
140 175 210
23 30
10 15
V
µA
µA
µA
µs
µs
LOGIC SUPPLY
Logic Input Voltage Level
Logic Input Current
VL
IVL
2.3 3.3 5.5
0.01 1
V
µA
DIGITAL I/O
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Input Capacitance
VIH
VIL
IIN GND VIN 5.5 V
CIN
VL ϫ 0.7
VL ϫ 0.3
±1
10
V
V
µA
pF
NOTES
1Swing error is a comparison of measured VOUT step versus theoretical VOUT step. Theoretical values can be found on the Mask Tap Point Option sheet.
2Mean error is measured VOUT mean versus theoretical VOUT mean (see Figure 3).
3Mean errors between two adjacent channels versus theoretical (see Figure 3).
4Mean errors between V0 and V4 versus theoretical (see Figure 3).
5Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1) .
Specifications subject to change without notice.
RL
100
CL
16nF
VCOM
Figure 1. Slew Rate Diagram
–2– REV. 0


Features a FEATURES Two Mask Programmable Sets of Five Reference Levels Dual 10-Bit DACs for Flicker Offset and Range Adjustmen t Integrated VCOM Switching Single-Supp ly Operation: 5.0 V Low Supply Current: 300 ␮ A Global Power Save Mode: 1 A Max Fast Settling Time for Load Chan ge: 20 ␮ s Stable with 20 nF/100 ⍀ Loads CMOS/TTL Input Levels APPLICATION S Color TFT Cell Phones Color TFT PDAs VL VDD VDD/2 VREF+ 10-BIT DAC A VREF– Integrated LCD Grayscale Generator AD D8502 FUNCTIONAL BLOCK DIAGRAM REV2 VDD VP0 VN0 R A0 V0 GND R VN4 R VP0 A1 V 1 MUX GENERAL DESCRIPTION SCK INTERF ACE LOGIC A2 DIGITAL CORE VP4 POWER SA VE LOGIC VN4 R VP4 A3 V2 The ADD8502 is an integrated, high accuracy, progra mmable grayscale generator. Two sets of five output reference voltages are mas k programmed to 0.2% resolution. The ou tputs switch between the two sets of fi ve levels. The reference levels are sel ected from a 512 tap resistor network u sing a via mask. ADD8502 includes two serially addressable, 10-bit digita.
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