X5328 EEPROM Datasheet

X5328 Datasheet, PDF, Equivalent


Part Number

X5328

Description

(X5328 / X5329) CPU Supervisor with 32Kbit SPI EEPROM

Manufacture

Intersil Corporation

Total Page 21 Pages
Datasheet
Download X5328 Datasheet


X5328
®
Data Sheet
X5328, X5329
(Replaces X25328, X25329)
October 17, 2005
FN8132.1
CPU Supervisor with 32Kbit SPI EEPROM
FEATURES
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<1µA max standby current
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lockprotection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
WP
SI
SO
SCK
CS
Data
Register
Command
Decode &
Control
Logic
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions by holding
RESET/RESET active when VCC falls below a mini-
mum VCC trip point. RESET/RESET remains asserted
until VCC returns to proper operating level and stabi-
lizes. Five industry standard VTRIP thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applica-
tions requiring higher precision.
Protect Logic
Status
Register
8Kbits
8Kbits
16Kbits
VCC
VTRIP
+
-
Reset
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5328 = RESET
X5329 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X5328
X5328, X5329
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5328P-4.5A
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5329P-4.5A
PART
MARKING
VCC RANGE
TEMP
(V) VTRIP RANGE RANGE (°C)
PACKAGE
4.5-5.5
4.5-4.75
0 to 70 8 Ld PDIP
X5328PZ-4.5A (Note) X5328P Z AL X5329PZ-4.5A (Note) X5329P Z AL
0 to 70 8 Ld PDIP (Pb-free)
X5328PI-4.5A
X5329PI-4.5A
-40 to 85 8 Ld PDIP
X5328PIZ-4.5A (Note) X5328P Z AM X5329PIZ-4.5A (Note) X5329P Z AM
-40 to 85 8 Ld PDIP (Pb-free)
X5328S8-4.5A
X5328 AL X5329S8-4.5A
0 to 70 8 Ld SOIC
X5328S8Z-4.5A (Note) X5328 Z AL X5329S8Z-4.5A (Note) X5329 Z AL
0 to 70 8 Ld SOIC (Pb-free)
X5328S8I-4.5A
X5328 AM X5329S8I-4.5A
-40 to 85 8 Ld SOIC
X5328S8IZ-4.5A
(Note)
X5328 Z AM X5329S8IZ-4.5A
(Note)
X5329 Z AM
-40 to 85 8 Ld SOIC (Pb-free)
X5328V14-4.5A
X5329V14-4.5A
0 to 70 14 Ld TSSOP
X5328V14Z-4.5A
(Note)
X5328V Z AL X5329V14Z-4.5A
(Note)
X5329V Z AL
0 to 70
14 Ld TSSOP
(Pb-free)
X5328V14I-4.5A
X5329V14I-4.5A
-40 to 85 14 Ld TSSOP
X5328V14IZ-4.5A
(Note)
X5328V Z AM X5329V14IZ-4.5A
(Note)
X5329V Z AM
-40 to 85 14 Ld TSSOP
(Pb-free)
X5328P
X5328P
X5329P
X5329P
4.5-5.5
4.25-4.5
0 to 70 8 Ld PDIP
X5328PZ (Note)
X5328P Z X5329PZ (Note)
X5329P Z
0 to 70 8 Ld PDIP (Pb-free)
X5328PI
X5328P I
X5329PI
X5329P I
-40 to 85 8 Ld PDIP
X5328PIZ (Note)
X5328P Z I X5329PIZ (Note)
X5329P Z I
-40 to 85 8 Ld PDIP (Pb-free)
X5328S8*
X5328
X5329S8*
0 to 70 8 Ld SOIC
X5328S8Z* (Note) X5328 Z
X5329S8Z* (Note) X5329 Z
0 to 70 8 Ld SOIC (Pb-free)
X5328S8I*
X5328 I
X5329S8I*
-40 to 85 8 Ld SOIC
X5328S8IZ* (Note) X5328 Z I X5329S8IZ* (Note) X5329 Z I
-40 to 85 8 Ld SOIC (Pb-free)
X5328V14*
X5328V
X5329V14*
0 to 70 14 Ld TSSOP
X5328V14Z* (Note) X5328V Z X5329V14Z* (Note) X5329V Z
X5328V14I*
X5328V14IZ* (Note)
X5328V Z I
X5329V14I*
X5329V14IZ* (Note)
X5329V Z I
X5328P-2.7A
X5329P-2.7A
X5328PZ-2.7A (Note) X5328P Z AN X5329PZ-2.7A (Note) X5329P Z AN
X5328PI-2.7A
X5329PI-2.7A
X5328PIZ-2.7A (Note) X5328P Z AP X5329PIZ-2.7A (Note) X5329P Z AP
X5328S8-2.7A
X5328 AN X5329S8-2.7A
X5328S8Z-2.7A (Note) X5328 Z AN X5329S8Z-2.7A (Note) X5329 Z AN
X5328S8I-2.7A
X5328 AP X5329S8I-2.7A
X5328S8IZ-2.7A
(Note)
X5328 Z AP X5329S8IZ-2.7A
(Note)
X5329 Z AP
X5328V14-2.7A
X5328V AN X5329V14-2.7A
X5328V14Z-2.7A
(Note)
X5328V Z AN X5329V14Z-2.7A
(Note)
X5329V Z AN
2.7-5.5
2.85-3.0
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
0 to 70
0 to 70
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
2 FN8132.1
October 17, 2005


Features ® X5328, X5329 (Replaces X25328, X2532 9) Data Sheet October 17, 2005 FN8132.1 CPU Supervisor with 32Kbit SPI EEPROM FEATURES • Low VCC detection and res et assertion —Five standard reset thr eshold voltages —Re-program low VCC r eset threshold voltage using special pr ogramming sequence —Reset signal vali d to VCC = 1V • Long battery life wit h low power consumption —<1µA max st andby current —<400µA max active cur rent during read • 32Kbits of EEPROM • Built-in inadvertent write protecti on —Power-up/power-down protection ci rcuitry —Protect 0, 1/4, 1/2 or all o f EEPROM array with Block Lock™ prote ction —In circuit programmable ROM mo de • 2MHz SPI interface modes (0,0 & 1,1) • Minimize EEPROM programming ti me —32-byte page write mode —Self-t imed write cycle —5ms write cycle tim e (typical) • 2.7V to 5.5V and 4.5V t o 5.5V power supply operation • Avail able packages —14 Ld TSSOP, 8 Ld SOIC , 8 Ld PDIP • Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM WP SI SO SCK CS Data Register Com.
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