SPI EEPROM. X5325 Datasheet

X5325 Datasheet PDF, Equivalent


Part Number

X5325

Description

(X5323 / X5325) CPU Supervisor with 32Kb SPI EEPROM

Manufacture

Intersil Corporation

Total Page 21 Pages
PDF Download
Download X5325 Datasheet PDF


X5325 Datasheet
®
Data Sheet
X5323, X5325
(Replaces X25323, X25325)
October 27, 2005
FN8131.1
CPU Supervisor with 32Kb SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lockprotection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SI
SO
SCK
CS/WDI
VCC
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
8Kbits
8Kbits
16Kbits
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5323 = RESET
X5325 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X5325 Datasheet
X5323, X5325
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5323P-4.5A
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
X5323P AL X5325P-4.5A
PART
MARKNIG
X5325P AL
VCC RANGE
TEMP
(V) VTRIP RANGE RANGE (°C)
PACKAGE
4.5-5.5
4.5-4.75
0 to 70 8 Ld PDIP
X5323PZ-4.5A (Note) X5323P Z AL X5325PZ-4.5A
X5325P Z AL
0 to 70 8 Ld PDIP (Pb-free)
X5323PI-4.5A
X5323P AM X5325PI-4.5A
X5325P AM
-40 to 85 8 Ld PDIP
X5323PIZ-4.5A (Note) X5323P Z AM X5325PIZ-4.5A
X5325P Z AM
-40 to 85 8 Ld PDIP (Pb-free)
X5323S8-4.5A
X5323 AL X5325S8-4.5A
X5325 AL
0 to 70 8 Ld SOIC
X5323S8Z-4.5A (Note) X5323 Z AL X5325S8Z-4.5A (Note) X5325 Z AL
0 to 70 8 Ld SOIC (Pb-free)
X5323S8I-4.5A*
X5323 AM X5325S8I-4.5A
X5325 AM
-40 to 85 8 Ld SOIC
X5323S8IZ-4.5A*
(Note)
X5323 Z AM X5325S8IZ-4.5A
(Note)
X5325 Z AM
-40 to 85 8 Ld SOIC (Pb-free)
X5323V14-4.5A
X5325V14-4.5A
0 to 70 14 Ld TSSOP
X5323V14Z-4.5A
(Note)
X5323V Z AL X5325V14Z-4.5A
(Note)
X5325V Z AL
0 to 70 14 Ld TSSOP
(Pb-free)
X5323V14I-4.5A
X5325V14I-4.5A
-40 to 85 14 Ld TSSOP
X5323V14IZ-4.5A
(Note)
X5323V Z AM X5325V14IZ-4.5A
(Note)
X5325V Z AM
-40 to 85 14 Ld TSSOP
(Pb-free)
X5323P
X5323P
X5325P
X5325P
4.5-5.5
4.25-4.5
0 to 70 8 Ld PDIP
X5323PZ (Note)
X5323P Z X5325PZ
X5325P Z
0 to 70 8 Ld PDIP (Pb-free)
X5323PI
X5323P I
X5325PI
X5325P I
-40 to 85 8 Ld PDIP
X5323PIZ (Note)
X5323P Z I X5325PIZ
X5325P Z I
-40 to 85 8 Ld PDIP (Pb-free)
X5323S8*
X5323
X5325S8*
X5325
0 to 70 8 Ld SOIC
X5323S8Z* (Note)
X5323 Z
X5325S8Z* (Note)
X5325 Z
0 to 70 8 Ld SOIC (Pb-free)
X5323S8I*
X5323 I
X5325S8I*
X5325 I
-40 to 85 8 Ld SOIC
X5323S8IZ* (Note) X5323 Z I X5325S8IZ* (Note) X5325 Z I
-40 to 85 8 Ld SOIC (Pb-free)
X5323V14*
X5323V
X5325V14*
0 to 70 14 Ld TSSOP
X5323V14Z* (Note) X5323V Z X5325V14Z* (Note) X5325V Z
X5323V14I*
X5323V14IZ* (Note)
X5323V Z I
X5325V14I*
X5325V14IZ* (Note)
X5325V Z I
X5323P-2.7A
X5323P AN X5325P-2.7A
X5325P AN
X5323PZ-2.7A (Note) X5323P Z AN X5325PZ-2.7A
X5325P Z AN
X5323PI-2.7A
X5323P AP X5325PI-2.7A
X5325P AP
X5323PIZ-2.7A (Note) X5323P Z AP X5325PIZ-2.7A
X5325P Z AP
X5323S8-2.7A*
X5323 AN X5325S8-2.7A
X5325 AN
X5323S8Z-2.7A*
(Note)
X5323 Z AN X5325S8Z-2.7A (Note) X5325 Z AN
X5323S8I-2.7A*
X5323 AP X5325S8I-2.7A
X5325 AP
X5323S8IZ-2.7A*
(Note)
X5323 Z AP X5325S8IZ-2.7A
(Note)
X5325 Z AP
2.7-5.5
2.85-3.0
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC
-40 to 85 8 Ld SOIC (Pb-free)
2 FN8131.1
October 27, 2005


Features Datasheet pdf ® X5323, X5325 (Replaces X25323, X2532 5) Data Sheet October 27, 2005 FN8131.1 CPU Supervisor with 32Kb SPI EEPROM F EATURES • Selectable watchdog timer Low VCC detection and reset assertio n —Five standard reset threshold volt ages —Re-program low VCC reset thresh old voltage using special programming s equence —Reset signal valid to VCC = 1V • Determine watchdog or low voltag e reset with a volatile flag bit • Lo ng battery life with low power consumpt ion —<50µA max standby current, watc hdog on —<1µA max standby current, w atchdog off —<400µA max active curre nt during read • 32Kbits of EEPROM Built-in inadvertent write protection —Power-up/power-down protection circ uitry —Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock™ protect ion —In circuit programmable ROM mode • 2MHz SPI interface modes (0,0 & 1, 1) • Minimize EEPROM programming time —32-byte page write mode —Self-tim ed write cycle —5ms write cycle time (typical) • 2.7V to 5.5V and 4.5V to 5.5V power supply operation • Ava.
Keywords X5325, datasheet, pdf, Intersil Corporation, X5323, /, X5325, CPU, Supervisor, with, 32Kb, SPI, EEPROM, 5325, 325, 25, X532, X53, X5, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




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