74ALS580 SN74ALS580 Datasheet

74ALS580 Datasheet PDF, Equivalent


Part Number

74ALS580

Description

SN74ALS580

Manufacture

ETC

Total Page 17 Pages
Datasheet
Download 74ALS580 Datasheet


74ALS580
SN54ALS580B, SN74ALS580B, SN74AS580
OCTAL DĆTYPE TRANSPARENT LATCHES
WITH 3ĆSTATE OUTPUTS
SDAS277 − JANUARY 1995
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
Inverting-Logic Outputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Flat
(W) Packages
description
These octal D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
SN54ALS580B . . . J OR W PACKAGE
SN74ALS580B, SN74AS580 . . . DW OR N PACKAGE
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
SN54ALS580B . . . FK PACKAGE
(TOP VIEW)
While the latch-enable (LE) input is high, outputs
(Q) respond to the data (D) inputs. When LE is low,
the outputs are latched to retain the data that was
set up.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
3D
3 2 1 20 19
4 18
2Q
4D 5
17 3Q
5D 6
16 4Q
6D 7
15 5Q
7D 8
14 6Q
9 10 11 12 13
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54ALS580B is characterized for operation over the full military temperature range of − 55°C to 125°C.
The SN74ALS580B and SN74AS580 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L HH
L
LHL
H
LLX
HXX
Q0
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1

74ALS580
SN54ALS580B, SN74ALS580B, SN74AS580
OCTAL DĆTYPE TRANSPARENT LATCHES
WITH 3ĆSTATE OUTPUTS
SDAS277 − JANUARY 1995
logic symbol
logic diagram (positive logic)
1
OE
11
LE
2
1D
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
EN
C1
1D
19
1Q
18
2Q
17
3Q
16
4Q
15
5Q
14
6Q
13
7Q
12
8Q
1
OE
11
LE
2
1D
C1
1D
19
1Q
To Seven Other Channels
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS580B . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74ALS580B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
VCC
VIH
VIL
IOH
IOL
tw
tsu
th
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Pulse duration, LE high
Setup time, data before LE
Hold time, data after LE
Operating free-air temperature
SN54ALS580B
MIN NOM MAX
4.5 5 5.5
2
0.7
−1
12
15
20
12
−55 125
SN74ALS580B
MIN NOM MAX
4.5 5 5.5
2
0.8
− 2.6
24
15
10
10
0 70
UNIT
V
V
V
mA
mA
ns
ns
ns
°C
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Features SN54ALS580B, SN74ALS580B, SN74AS580 OCTA L DĆTYPE TRANSPARENT LATCHES WITH 3ĆS TATE OUTPUTS SDAS277 − JANUARY 1995 • 3-State Buffer-Type Outputs Drive B us Lines Directly • Bus-Structured Pi nout • Inverting-Logic Outputs • Pa ckage Options Include Plastic Small-Out line (DW) Packages, Ceramic Chip Carrie rs (FK), Standard Plastic (N) and Ceram ic (J) 300-mil DIPs, and Ceramic Flat ( W) Packages description These octal D-t ype transparent latches feature 3-state outputs designed specifically for driv ing highly capacitive or relatively low -impedance loads. They are particularly suitable for implementing buffer regis ters, I/O ports, bidirectional bus driv ers, and working registers. SN54ALS580 B . . . J OR W PACKAGE SN74ALS580B, SN7 4AS580 . . . DW OR N PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE SN54ALS580B . . . FK PACKAGE (TOP VIEW ) 8D 2D GND 1D LE OE 8Q VCC 7Q 1Q While the latch-enable (LE) input is hi.
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