BUS-61556-xxxx Hybrid Datasheet

BUS-61556-xxxx Datasheet, PDF, Equivalent


Part Number

BUS-61556-xxxx

Description

Advanced Integrated MUX Hybrid

Manufacture

Data Device

Total Page 4 Pages
Datasheet
Download BUS-61556-xxxx Datasheet


BUS-61556-xxxx
BUS-61553
eet4UM.cIoLm-STD-1553 ADVANMCUEXD(IANIMTE)GHRYABTREIDDUSSEERE’SALGSUOIDE
ShDESCRIPTION
taDDC’s BUS-61553 Advanced
aIntegrated Mux (AIM) Hybrid is a
.Dcomplete MIL-STD-1553 Bus
Controller (BC), Remote Terminal
wUnit (RTU), and Bus Monitor (MT)
wdevice. Packaged in a single 78-pin
wDIP package, the BUS-61553 con-
tains dual low-power transceivers,
mcomplete BC/RT/MT protocol logic, a
oMIL-STD-1553-to-host interface unit
and 8K x 16 RAM.
.cUsing an industry standard dual
transceiver and standard status and
control signals, the BUS-61553 sim-
Uplifies system integration at both the
t4MIL-STD-1553 and host processor
interface levels.
eAll 1553 operations are controlled
through the CPU access to the
shared 8K x 16 RAM. To ensure
maximum design flexibility, memory
control lines are provided for attach-
ing external RAM to the BUS-61553
address and data buses and for dis-
abling internal memory; the total
combined memory space can be
expanded to 64K x 16. All 1553 trans-
fers are entirely memory-mapped;
thus the CPU interface requires
minimal hardware and/or software
support.
The BUS-61553 operates over the
full military -55°C to +125°C temper-
ature range. Available screened to
MIL-PRF-38534, the BUS-61553 is
ideal for demanding military and
industrial microprocessor-to-1553
interface applications.
FEATURES
• Fully Intergrated Terminal
Including:
–Dual Transceiver
–BC/RT/MT Protocol
–Memory Management Unit
–Processor lnterface Logic
–8K x 16 RAM
• CMOS and Bipolar Technologies
• Internal Interrupt Status and Time
Tag Registers
• High Reliability
• 883B Processing Available
heBUS-25679
S8 1
DATA
taBUSA 4
2
3
w.DaTRANSFORMER A
TRANSCEIVER A
TX INH
TX CHANNEL A
ENCODER/
RX DECODER
RX
MEMORY
TIMING
768 µs
TIME OUT
PROTOCOL
CONTROLLER
CONTENTION
RESOLVER
CPU
TIMING
INTERRUPT
GENERATOR
CLOCK IN
MSTRCLR
SELECT
STRBD
READYD
RD/WR
MEM/REG
EXTEN
EXTLD
INT
w mBUS-25679
w .coDATA
BUS B
8
4
1
2
3
.DataSheet4UTRANSFORMER B
A15-A00
TX INH
D15-D00
TX CHANNEL B
ENCODER/
RX DECODER
RX
TRANSCEIVER B
8K x 16
SHARED RAM
RAM
PARITY
CHECKER
RT ADDR
FIGURE 1. BU-61553 BLOCK DIAGRAM
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RTAD P
RTPARERR
www© 1987, 1999 Data Device Corporation

BUS-61556-xxxx
ORDERING INFORMATION
BUS-615XX- XX0X
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See Page 13.)
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See Page 13.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Power Supply
3 = -15 V Transceivers
4 = -12 V Transceivers
5 = +5 V Transceivers–Call Factory
6 = Transceivers–Use with BUS-63102II–Call Factory
Packaging
5 = DDIP
6 = Flat Pack
2


Features m o MIL-STD-1553 ADVANCED INTEGRATED .c U MUX (AIM ) HYBRID SO L 4 A E E t S E e S GUID ’ R E S U e h DESCRIPTION S FEATURES a • Fully Intergrated Termin al at Including: .D –Dual Transceiver w –BC/RT/MT Protocol w –Memory Man agement Unit w –Processor lnterface L ogic DDC’s BUS-61553 Advanced Integra ted Mux (AIM) Hybrid is a complete MIL- STD-1553 Bus Controller (BC), Remote Te rminal Unit (RTU), and Bus Monitor (MT) device. Packaged in a single 78-pin DI P package, the BUS-61553 contains dual low-power transceivers, complete BC/RT/ MT protocol logic, a MIL-STD-1553-to-ho st interface unit and 8K x 16 RAM. Usin g an industry standard dual transceiver and standard status and control signal s, the BUS-61553 simplifies system inte gration at both the MIL-STD-1553 and ho st processor interface levels. All 1553 operations are controlled through the CPU access to the BUS-61553 BUS-25679 8 1 DATA BUS A 2 4 3 TRANSFORMER A B US-25679 8 DATA BUS B 4 1 2 3 m o .c U 4 t e e h S a t a .D w w w –8K x 16 R.
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