BUS-61560-xxxx Terminal Datasheet

BUS-61560-xxxx Datasheet, PDF, Equivalent


Part Number

BUS-61560-xxxx

Description

MIL-STD-1553 Bc-rt-mt Integrated Terminal

Manufacture

Data Device

Total Page 4 Pages
Datasheet
Download BUS-61560-xxxx Datasheet


BUS-61560-xxxx
BUS-61559 SERIES
MIL-STD-1553B NOTICE 2
ADVANCED INTEGRATED MUX HYBRIDS
WITH ENHANCED RT FEATURES (AIM-HY’er)
DESCRIPTION
DDC’s BUS-61559 series of Advanced buffers to provide a direct interface to
Integrated Mux Hybrids with enhanced a host processor bus. Alternatively,
RT Features (AIM-HY’er) comprise a the buffers may be operated in a fully
complete interface between a micro- transparent mode in order to interface
processor and a MIL-STD-1553B to up to 64K words of external shared
Notice 2 bus, implementing Bus RAM and/or connect directly to a com-
Controller (BC), Remote Terminal (RX, ponent set supporting the 20 MHz
and Monitor Terminal (MT) modes. STANAG-3910 bus.
Packaged in a single 78-pin DIP or
82-pin flat package the BUS-61559 The memory management scheme
series contains dual low-power trans- for RT mode prevails an option for
ceivers and encoder/decoders, com- separation of broadcast data, in com-
plete BC/RT/MT protocol logic, memory pliance with 1553B Notice 2. A circu-
management and interrupt logic, 8K x 16 lar buffer option for RT message data
of shared static RAM, and a direct, blocks offloads the host processor for
buffered interface to a host processor bus. bulk data transfer applications.
The BUS-61559 includes a number of
advanced features in support of
MIL-STD-1553B Notice 2 and STANAG
Another feature besides those listed
to the right, is a transmitter inhibit con-
trol for the individual bus channels.
3838. Other salient features of the The BUS-61559 series hybrids oper-
BUS-61559 serve to provide the bene- ate over the full military temperature
fits of reduced board space require- range of -55 to +125”C and MIL-PRF-
ments enhanced software flexibility, 38534 processing is available. The
and reduced host processor overhead hybrids are ideal for demanding mili-
The BUS-61559 contains internal
address latches and bidirectional data
tary and industrial microprocessor-to-
1553 applications
FEATURES
Complete Integrated 1553B
Notice 2 Interface Terminal
Functlonal Superset of BUS-
61553 AlM-HYSeries
Internal Address and Data
Buffers for Dlrect Interface to
Processor Bus
RT Subaddress Circular Buffers
to Support Bulk Data Transfers
Optlonal Separatlon of
RT Broadcast Data
Internal Interrupt Status and
Time Tag Registers
Internal ST Command
Illegalization
MIL-PRF-38534 Processing
Available
(ILLEGALIZATION ILLENA
ENABLE)
ILLEGALLIZATION
LOGIC
BUS-25679
81
7
5
2
43
LOW-POWER
TRANSCEIVER
A
8K x 16
DUAL
PORT
RAM
CLK IN (16MHz)
TX_INH_A
BUS-25679
81
7
5
2
43
LOW-POWER
TRANSCEIVER
A
DUAL
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
TX_INH_A
(RT ADDRESS)
RTAD 4-, RTADP
(BROADCAST
ENABLE)
(RTFAIL,
RTFLAG)
(BROADCAST,
MESSAGE
TIMING, DATA
STROBE AND ERROR
INDICATORS)
BRO_ENA
RTFAIL
RTFLAG
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
MEMORY DATA
DATA
BUFFERS*
D15-D
(PROCESSOR
DATA)
MEMORY ADDRESS
ADDRESS
LATCHES/
BUFFERS*
A15-A
(PROCESSOR
ADDRESS)
ADDR_LAT (ADDRESS
LATCH
CONTROL)
MEMORY
MANAGEMENT,
SHARED
RAM/
PROCESSOR
INTERFACE,
INTERRUPT
LOGIC
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
IOEN, READYD
(PROCESSOR
CONTROL)
INT
MEMEN-OUT,MEMWR, MEMOE
MEMENA-IN
(INTERRUPT
REQUEST)
(MEMORY
CONTROL)
SSFLAG
TAGCLK
(SUBSYSTEM
FLAG)
(TIME TAG
CLOCK)
BU-61559 BLOCK DIAGRAM
© 1990, 1999 Data Device Corporation

BUS-61560-xxxx
ORDERING INFORMATION
BUS-615XX- XX0X*
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See page xiii.)
1 = MIL-PRF-38534 Compliant
2 = B**
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B** with PIND Testing
7 = B** with Solder Dip
8 = B** with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See page xiii.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Power Supply and Packaging
59 = +5 V/-15 V DDIP
60 = +5 V/-12 V DIP
69 = +5 V/-15 V Flat Pack
70 = +5 V/-12 V Flat Pack
71 = +5 V Flat Pack
*-601 version also available = MIL-STD-1760 compatible with fully compliant
MIL-PRF-38534 Processing Available
2


Features BUS-61559 SERIES MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH EN HANCED RT FEATURES (AIM-HY’er) DESCRI PTION DDC’s BUS-61559 series of Advan ced Integrated Mux Hybrids with enhance d RT Features (AIM-HY’er) comprise a complete interface between a microproce ssor and a MIL-STD-1553B Notice 2 bus, implementing Bus Controller (BC), Remot e Terminal (RX, and Monitor Terminal (M T) modes. Packaged in a single 78-pin D IP or 82-pin flat package the BUS-61559 series contains dual low-power transce ivers and encoder/decoders, complete BC /RT/MT protocol logic, memory managemen t and interrupt logic, 8K x 16 of share d static RAM, and a direct, buffered in terface to a host processor bus. The BU S-61559 includes a number of advanced f eatures in support of MIL-STD-1553B Not ice 2 and STANAG 3838. Other salient fe atures of the BUS-61559 serve to provid e the benefits of reduced board space r equirements enhanced software flexibili ty, and reduced host processor overhead buffers to provide a direct i.
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