PC7447 Microprocessor Datasheet

PC7447 Datasheet, PDF, Equivalent


Part Number

PC7447

Description

(PC7447 / PC7457) PowerPC 7457 RISC Microprocessor

Manufacture

ATMEL Corporation

Total Page 30 Pages
Datasheet
Download PC7447 Datasheet


PC7447
Features
3000 Dhrystone 2.1 MIPS at 1.3 GHz
Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
13 Selectable Core-to-L3 Frequency Divisors
Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
Selectable L3 Interface of 1.8V or 2.5V
PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating
Conditions
Nap, Doze and Sleep Modes for Power Saving
Superscalar (Four Instructions Fetched Per Clock Cycle)
4 GB Direct Addressing Range
Virtual Memory: 4 Hexabytes (252)
64-bit Data and 32-bit Address Bus Interface
Integrated L1: 32 KB Instruction and 32 KB Data Cache
Integrated L2: 512 KB
11 Independent Execution Units and Three Register Files
Write-back and Write-through Operations
fINT Max = 1 GHz (1.2 GHz to be Confirmed)
fBUS Max = 133 MHz/166 MHz
Description
This document is primarily concerned with the PowerPCPC7457; however, unless
otherwise noted, all information here also applies to the PC7447. The PC7457 and
PC7447 are implementations of the PowerPC microprocessor family of reduced
instruction set computer (RISC) microprocessors. This document describes pertinent
electrical and physical characteristics of the PC7457.
The PC7457 is the fourth implementation of the fourth generation (G4) microproces-
sors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and
is targeted at networking and computing systems applications. The PC7457 consists
of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which sup-
port a glueless backside L3 cache through a dedicated high-bandwidth interface. The
PC7447 is identical to the PC7457 except it does not support the L3 cache interface.
The core is a high-performance superscalar design supporting a double-precision
floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-
ports the MPX bus interface to main memory and other system resources. The L3
interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private
memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes
may be used as cache; the remaining 2M bytes must be private memory.
Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455
application if the core power supply is 1.3V.
PowerPC 7457
RISC
Microprocessor
PC7457/47
Preliminary
Specification
α-site
Rev. 5345B–HIREL–02/04

PC7447
Screening
• CBGA Upscreenings Based on Atmel Standards
• Full Military Temperature Range (Tj = -55°C, +125°C),
Industrial Temperature Range (Tj = -40°C, +110°C)
• CBGA Package, HiTCE Package for the 7447 TBC
CBGA 483
G suffix
CBGA 360
Ceramic Ball Grid Array
GH suffix
HITCE 360
Ceramic Ball Grid Array (TBC)
2 PC7457/47 [Preliminary]
5345B–HIREL–02/04


Features Features • • • • • • • • • • • • • • • • • 30 00 Dhrystone 2.1 MIPS at 1.3 GHz Select able Bus Clock (30 CPU Bus Dividers up to 28x) 13 Selectable Core-to-L3 Freque ncy Divisors Selectable MPx/60x Interfa ce Voltage (1.8V, 2.5V) Selectable L3 I nterface of 1.8V or 2.5V PD Typical 12. 6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GH z at VDD = 1.1V, Full Operating Conditi ons Nap, Doze and Sleep Modes for Power Saving Superscalar (Four Instructions Fetched Per Clock Cycle) 4 GB Direct Ad dressing Range Virtual Memory: 4 Hexaby tes (252) 64-bit Data and 32-bit Addres s Bus Interface Integrated L1: 32 KB In struction and 32 KB Data Cache Integrat ed L2: 512 KB 11 Independent Execution Units and Three Register Files Write-ba ck and Write-through Operations fINT Ma x = 1 GHz (1.2 GHz to be Confirmed) fBU S Max = 133 MHz/166 MHz PowerPC 7457 R ISC Microprocessor PC7457/47 Preliminar y Specification α-site Description Th is document is primarily concerned with the PowerPC™ PC7457; however, unless otherwise noted, all .
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