Z80380 Datasheet: Microprocessor

Z80380 Microprocessor Datasheet

Part Number Z80380
Description Microprocessor
Manufacture Zilog
Total Page 30 Pages
PDF Download Download Z80380 Datasheet PDF

Features: ZILOG MICROPROCESSOR FEATURES s w s s a D . Static CMOS Design with Low-Pow er Standby Mode w wOption 32-Bit Intern al Data Paths and ALU Operating Frequen cy - DC-to-18 MHz at 5V - DC-to-10 MHz at 3.3V Enhanced Instruction Set that M aintains Object-Code Compatibility with Z80® and Z180™ Microprocessors 16-B it (64K) or 32-Bit (4G) Linear Address Space 16-Bit Data Bus with Dynamic Sizi ng S a t e e h U 4 t m o .c PRODUC T SPECIFICATION Z380™ MICROPROCESSOR s s s Two-Clock Cycle Instruction Exe cution Minimum Four Banks of On-Chip Re gister Files Enhanced Interrupt Capabi lities, Including 16-Bit Vector Undefin ed Opcode Trap for Z380™ Instruction Set On-Chip I/O Functions: - Six-Memory Chip Selects with Programmable Waits - Programmable I/O Waits - DRAM Refresh Controller 100-Pin QFP Package s s s s s GENERAL DESCRIPTION The Z380™ Microprocessor is an integrated highper formance microprocessor with fast and e fficient throughput and increased memory addressing capabilities. The Z3.

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ataSheet4U.co Z380FEATURES
.Ds Static CMOS Design with Low-Power Standby Mode
wws 32-Bit Internal Data Paths and ALU
ms Operating Frequency
o- DC-to-18 MHz at 5V
.c- DC-to-10 MHz at 3.3V
s Enhanced Instruction Set that Maintains Object-Code
UCompatibility with Z80® and Z180Microprocessors
t4s 16-Bit (64K) or 32-Bit (4G) Linear Address Space
es 16-Bit Data Bus with Dynamic Sizing
s Two-Clock Cycle Instruction Execution Minimum
s Four Banks of On-Chip Register Files
s Enhanced Interrupt Capabilities, Including
16-Bit Vector
s Undefined Opcode Trap for Z380Instruction Set
s On-Chip I/O Functions:
- Six-Memory Chip Selects with Programmable Waits
- Programmable I/O Waits
- DRAM Refresh Controller
s 100-Pin QFP Package
SThe Z380Microprocessor is an integrated high-
taperformance microprocessor with fast andefficientthrough-
put and increased memory addressing capabilities. The
aZ380offers a continuing growth path for present Z80-or
Z180-based designs, while maintaining Z80® CPU and
Z180® MPU object-code compatibility. The Z380MPU
.Denhancements include an improved 280 CPU, expanded
4-Gbyte space and flexible bus interface timing.
wAn enhanced version of the Z80 CPU is key to the Z380
MPU. The basic addressing modes of the Z80 micropro-
wcessor have been augmented as follows: Stack Pointer
mRelative loads and stores, 16-bit and 24-bit indexed off-
w osets, and more flexible Indirect Register addressing, with
www.DataSheet4U.call of the addressing modes allowing access to the entire
32-bit address space. Additions made to the instruction
set, include a full complement of 16-bit arithmetic and
logical operations, 16-bit I/O operations, multiply and
divide, plus a complete set of register-to-register loads
and exchanges.
The expanded basic register file of the Z80 MPU micropro-
cessor includes alternate register versions of the IX and IY
registers. There are four sets of this basic Z80 micropro-
cessor register file present in the Z380 MPU, along with the
necessary resources to manage switching between the
different register sets. All of the register-pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.


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