ADSP21990 Controller Datasheet

ADSP21990 Datasheet, PDF, Equivalent


Part Number

ADSP21990

Description

Mixed Signal DSP Controller

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADSP21990 Datasheet


ADSP21990
PRELIMINARY TECHNICAL DATA
aPrelitamSinheaeryt4TUe.ccohmnical Data Mixed Signal DASDPSPC-o2n1t9r9o0llerMIXED SIGNAL DSP CONTROLLER FEATURES
ADSP-219x, 16-bit, Fixed Point DSP Core with up to 160
aMIPS sustained performance
.D8K Words of On chip RAM, Configured as 4K Words On
wchip 24-bit Program RAM and 4K Words On chip 16-bit
Data RAM
w External Memory Interface
w Dedicated Memory DMA Controller for Data/Instruction
mTransfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
oCircuitry Enables Full speed Operation from Low
speed Input Clocks
.cIEEE JTAG Standard 1149.1 Test Access Port Supports
On chip Emulation and System Debugging
8-Channel, 20 MSPS, 14-bit Analog to Digital Converter
USystem
Three Phase 16-bit Center Based PWM Generation Unit
with 12.5 ns resolution
Dedicated 32-bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-bit Auxiliary PWM Outputs
16 General Purpose Flag I/O Pins
Three Programmable 32-bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
Precision 1.0V Voltage Reference
Integrated Power-On-Reset (POR) Generator
t4FUNCTIONAL BLOCK DIAGRAM
SheeJTAG
TEST &
taEMULATION
CLOCK
GENERATOR / PLL
160 MHZ
ADSP-219X
DSP
aI/O
BUS
w.DI/O REGISTERS
4K X 24
PM RAM
(BLOCK 0)
4K X 16
DMRAM
(BLOCK 1)
4K X 24
PMROM
(BLOCK 2)
PM ADDRESS/DATA
DM ADDRESS/DATA
EXTERNAL
MEMORY
INTERFACE
(EMI)
ADDRESS
DATA
CONTROL
MEMORY DMA
CONTROLLER
ww omTIMER0
ADC CONTROL
PWM
ENCODER AUXILIARY
INTERRUPT
.cGENERATION INTERFACE
PWM
TIMER 1
FLAG
SPI
SPORT
WATCHDOG CONTROLLER
UUNIT
UNIT
(AND EET)
UNIT
TIMER 2
I/O
TIMER
(ICNTL)
PIPELINE
t4FLASH ADC
heePOR
VREF
ataSREV. PrA
w.DThis information applies to a product under development. Its characteristics and specifi- One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
cations are subject to change without notice. Analog Devices assumes no obligation Tel:781/329-4700
www.analog.com
wwregarding future manufacturing unless otherwise agreed to in writing.
Fax:781/326-8703
©Analog Devices,Inc., 2002

ADSP21990
PRELIMINARY TECHNICAL DATA
ADSP-21990
For current information contact Analog Devices at (781) 937-1799
February 2002
Flexible Power Management with Selectable Powerdown
and Idle Modes
2.5V Internal Operation with 3.3V I/O
Operating Temperature Range of –40ºC to 85ºC
196 ball mini-BGA package
TARGET APPLICATIONS
Industrial Motor Drives
Un-Interruptible Power Supplies
Optical Networking Control
Data Acquisition Systems
Test and Measurement Systems
Portable Instrumentation
GENERAL NOTE
This data sheet provides preliminary information for the
ADSP-21990 Mixed Signal Digital Signal Processor.
GENERAL DESCRIPTION
The ADSP-21990 is a mixed signal DSP controller based
on the ADSP-219x DSP Core, suitable for a variety of high
performance Industrial Motor Control and Signal Process-
ing applications that require the combination of a high
performance DSP and the mixed signal integration of
embedded control peripherals such as analog to digital
conversion.
The ADSP-21990 integrates the 160 MIPS, fixed point
ADSP-219x family base architecture with a serial port, an
SPI compatible port, a DMA controller, three programma-
ble timers, general purpose Programmable Flag pins,
extensive interrupt capabilities, on chip program and data
memory spaces, and a complete set of embedded control
peripherals that permits fast motor control and signal pro-
cessing in a highly integrated environment.
The ADSP-21990 architecture is code compatible with
previous ADSP-217x based ADMCxxx products. Although
the architectures are compatible, the ADSP-21990, with
ADSP-219x architecture, has a number of enhancements
over earlier architectures. The enhancements to computa-
tional units, data address generators, and program
sequencer make the ADSP-21990 more flexible and easier
to program than the previous ADSP-21xx embedded DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an
immediate 8-bit, two’s complement value and base address
registers for easier implementation of circular buffering.
The ADSP-21990 integrates 8K words of on chip memory
configured as 4K words (24-bit) of program RAM, and 4K
words (16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21990 operates with a 6.25 ns instruction cycle time
(160 MIPS). All instructions, except two multiword
instructions, execute in a single DSP cycle.
The ADSP-21990’s flexible architecture and comprehen-
sive instruction set support multiple operations in parallel.
For example, in one processor cycle, the ADSP-21990 can:
Generate an address for the next instruction fetch
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
These operations take place while the processor
continues to:
Receive and transmit data through the serial port
Receive or transmit data over the SPI port
Access external memory through the external memory
interface
Decrement the timers
Operate the embedded control peripherals (ADC, PWM,
EIU, etc.)
2 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrA


Features PRELIMINARY TECHNICAL DATA . a U t4 m o c w w e e Preliminary Technical Da ta h S a at .D w MIXED SIGNAL DSP CONTR OLLER FEATURES ADSP-219x, 16-bit, Fixed Point DSP Core with up to 160 MIPS sus tained performance 8K Words of On chip RAM, Configured as 4K Words On chip 24- bit Program RAM and 4K Words On chip 16 -bit Data RAM External Memory Interface Dedicated Memory DMA Controller for Da ta/Instruction Transfer between Interna l/External Memory Programmable PLL and Flexible Clock Generation Circuitry Ena bles Full speed Operation from Low spee d Input Clocks IEEE JTAG Standard 1149. 1 Test Access Port Supports On chip Emu lation and System Debugging 8-Channel, 20 MSPS, 14-bit Analog to Digital Conve rter System Mixed Signal DSP Controlle r ADSP-21990 Three Phase 16-bit Center Based PWM Generation Unit with 12.5 ns resolution Dedicated 32-bit Encoder Int erface Unit with Companion Encoder Even t Timer Dual 16-bit Auxiliary PWM Outpu ts 16 General Purpose Flag I/O Pins Three Programmable 32-bit I.
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