ADSP-21992 Controller Datasheet

ADSP-21992 Datasheet, PDF, Equivalent


Part Number

ADSP-21992

Description

Mixed Signal DSP Controller

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADSP-21992 Datasheet


ADSP-21992
ataSheet4U.com Mixed Signal DSP ContrAoDllSePr-W21it9h9C2ANKEY FEATURES
ADSP-219x, 16-Bit, Fixed Point DSP Core with up to
a160 MIPS Sustained Performance
.D48K Words of On-Chip RAM, Configured as 32K Words
wOn-Chip 24-Bit Program RAM and 16K Words On-Chip
16-Bit Data RAM
w External Memory Interface
w Dedicated Memory DMA Controller for Data/Instruction
mTransfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
oCircuitry Enables Full-Speed Operation from Low-
Speed Input Clocks
.cIEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
8-Channel, 14-Bit Analog-to-Digital Converter System,
Uwith up to 20 MSPS Sampling Rate (at 160 MHz Core
t4Clock Rate)
Three Phase 16-Bit Center Based PWM Generation Unit
with 12.5 ns Resolution at 160 MHz Core Clock (CCLK)
Rate
Dedicated 32-Bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-Bit Auxiliary PWM Outputs
16 General-Purpose Flag I/O Pins
Three Programmable 32-Bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Controller Area Network (CAN) Module Fully Compliant
with V2.0B Standard
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
eFUNCTIONAL BLOCK DIAGRAM
eCLOCK
GENERATOR/PLL
ShJTAG
taTEST AND
EMULATION
ADSP-219x
DSP CORE
.DaI/O
BUS
wwI/O REGISTERS
32K ؋ 24
PM RAM
16K ؋ 16
DM RAM
4K ؋ 24
PM ROM
PM ADDRESS/DATA
DM ADDRESS/DATA
SPI
EXTERNAL
MEMORY
INTERFACE
(EMI)
ADDRESS
DATA
CONTROL
SPORT
CONTROLLER AREA
NETWORK (CAN)
MEMORY DMA
CONTROLLER
w .comPWM
GENERATION
eet4UUNIT
ENCODER
INTERFACE
UNIT
(AND EET)
AUXILIARY
PWM
UNIT
TIMER 0
TIMER 1
TIMER 2
FLAG
I/O
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
(ICNTL)
ADC
CONTROL
POR
PIPELINE
FLASH ADC
VREF
ataShREV. 0
.DInformation furnished by Analog Devices is believed to be accurate and
wreliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
wmay result from its use. No license is granted by implication or otherwise
wunder any patent or patent rights of Analog Devices. Trademarks and
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
registered trademarks are the property of their respective companies.
Fax:781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.

ADSP-21992
ADSP-21992
KEY FEATURES (continued)
Precision 1.0 V Voltage Reference
Integrated Power-On-Reset (POR) Generator
Flexible Power Management with Selectable Power-
Down and Idle Modes
2.5 V Internal Operation with 3.3 V I/O
Operating Temperature Ranges of –40ºC to +85ºC and
–40ºC to +125ºC
196-Ball Mini-BGA Package
176-Lead LQFP Package
TARGET APPLICATIONS
Industrial Motor Drives
Uninterruptible Power Supplies
Optical Networking Control
Data Acquisition Systems
Test and Measurement Systems
Portable Instrumentation
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 4
External (Off-chip) Memory . . . . . . . . . . . . . . . . . . 5
External Memory Space . . . . . . . . . . . . . . . . . . . . . 5
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5
Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . 6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . 6
Serial Peripheral Interface (SPI) Port . . . . . . . . . . . . . 7
DSP Serial Port (SPORT) . . . . . . . . . . . . . . . . . . . . . 7
Controller Area Network (CAN) Module . . . . . . . . . 8
Analog-to-Digital Conversion System . . . . . . . . . . . . 8
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PWM Generation Unit . . . . . . . . . . . . . . . . . . . . . . . 9
Auxiliary PWM Generation Unit . . . . . . . . . . . . . . . . 9
Encoder Interface Unit . . . . . . . . . . . . . . . . . . . . . . 10
Flag I/O (FIO) Peripheral Unit . . . . . . . . . . . . . . . . 10
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . 11
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Peripheral Interrupt Controller . . . . . . . . . . . . . . . . 11
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 12
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-Down Core Mode . . . . . . . . . . . . . . . . . . . 12
Power-Down Core/Peripherals Mode . . . . . . . . . . 12
Power-Down All Mode . . . . . . . . . . . . . . . . . . . . 12
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset and Power-On Reset (POR) . . . . . . . . . . . . . . 13
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction Set Description . . . . . . . . . . . . . . . . . . . 14
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 14
Designing an Emulator-Compatible DSP Board . . . 15
Additional Information . . . . . . . . . . . . . . . . . . . . . . 15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 28
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 28
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 28
Clock In and Clock Out Cycle Timing . . . . . . . . . 29
Programmable Flags Cycle Timing . . . . . . . . . . . 30
Timer PWM_OUT Cycle Timing . . . . . . . . . . . . 31
External Port Write Cycle Timing . . . . . . . . . . . . 32
External Port Read Cycle Timing . . . . . . . . . . . . 33
External Port Bus Request/Grant Cycle Timing . . 34
Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial Peripheral Interface Port—Master Timing . 38
Serial Peripheral Interface Port—Slave Timing . . 39
JTAG Test And Emulation Port Timing . . . . . . . 40
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . 41
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 42
Example System Hold Time Calculation . . . . . . . 42
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 42
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 48
GENERAL DESCRIPTION
The ADSP-21992 is a mixed signal DSP controller based on the
ADSP-219x DSP Core, suitable for a variety of high performance
industrial motor control and signal processing applications that
require the combination of a high performance DSP and the
mixed signal integration of embedded control peripherals such
as analog-to-digital conversion with communications interfaces
such as CAN.
The ADSP-21992 integrates the fixed point ADSP-219x family
base architecture with a serial port, an SPI compatible port, a
DMA controller, three programmable timers, general-purpose
Programmable Flag pins, extensive interrupt capabilities, on-
chip program and data memory spaces, and a complete set of
embedded control peripherals that permits fast motor control
and signal processing in a highly integrated environment.
The ADSP-21992 architecture is code compatible with previous
ADSP-217x based ADMCxxx products. Although the architec-
tures are compatible, the ADSP-21992, with ADSP-219x
architecture, has a number of enhancements over earlier archi-
tectures. The enhancements to computational units, data address
generators, and program sequencer make the ADSP-21992 more
flexible and easier to program than the previous ADSP-21xx
embedded DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, twos complement value and base address registers for easier
implementation of circular buffering.
The ADSP-21992 integrates 48K words of on-chip memory con-
figured as 32K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21992 operates with a 6.25 ns instruction cycle time for
a 160 MHz CCLK, with a 6.67 ns instruction cycle time for a
–2– REV. 0


Features m o .c U 4 t e e h S a at .D w w w a M ixed Signal DSP Controller With CAN ADS P-21992 Three Phase 16-Bit Center Based PWM Generation Unit with 12.5 ns Resol ution at 160 MHz Core Clock (CCLK) Rate Dedicated 32-Bit Encoder Interface Uni t with Companion Encoder Event Timer Du al 16-Bit Auxiliary PWM Outputs 16 Gene ral-Purpose Flag I/O Pins Three Program mable 32-Bit Interval Timers SPI Commun ications Port with Master or Slave Oper ation Synchronous Serial Communications Port (SPORT) Capable of Software UART Emulation Controller Area Network (CAN) Module Fully Compliant with V2.0B Stan dard Integrated Watchdog Timer Dedicate d Peripheral Interrupt Controller with Software Priority Control Multiple Boot Modes KEY FEATURES ADSP-219x, 16-Bit, Fixed Point DSP Core with up to 160 MI PS Sustained Performance 48K Words of O n-Chip RAM, Configured as 32K Words On- Chip 24-Bit Program RAM and 16K Words O n-Chip 16-Bit Data RAM External Memory Interface Dedicated Memory DMA Controller for Data/Instruction .
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