LAN Controller. 21041-PB Datasheet

21041-PB Controller. Datasheet pdf. Equivalent

21041-PB Datasheet
Recommendation 21041-PB Datasheet
Part 21041-PB
Description PCI Ethernet LAN Controller
Feature 21041-PB; w w a D . w S a t e e h U 4 t .c om Digital Semiconductor 21041 PCI Ethernet LAN Controller .
Manufacture Digital
Download 21041-PB Datasheet

Digital 21041-PB
Digital Semiconductor 21041
m PCI Ethernet LAN Controller Product Brief
February 1996
Shee Description
ata The Digital Semiconductor 21041 PCI Ethernet LAN Controller is a single-chip
master, direct memory access (DMA) Ethernet LAN controller with a direct inter-
.D face to the PCI local bus. It supports full-duplex operation, and its unique design
w is optimized to reduce the host bus utilization.
w The 21041 is highly integrated to support 10BASE5, 10BASE-T, or 10BASE2
w network connections. It is a high-performance device designed for PCI-based sys-
tems. The 21041 provides a direct interface to a 64KB, 128KB or 256KB boot
mROM. It supports both PCI 3.3-volt and 5.0-volt signaling environments and a
power-down mode for energy conservation. The 21041 is supported by a variety
oof software drivers and therefore offers a complete solution for all the leading net-
.cworking environments.
UOffers a single-chip Ethernet control-
ler for PCI local bus:
t4- Provides glueless connection to PCI
- Contains an onchip integrated attach-
ement unit interface (AUI) port and a
e10BASE-T transceiver
Implements the same architecture as
hthe 21040 to allow use of unified driv-
SSupports full-duplex operation and
IEEE 802.3 autonegotiation algorithm
taof full-duplex and half-duplex net-
work environments*
aProvides upgradable boot ROM (flash
or EEPROM) interface of 64KB,
128KB, or 256KB*
.DContains MicroWire EEPROM inter-
face for Ethernet ID address and, op-
tionally, other system parameters*
w - Implements automatic loading of
subsystem vendor ID and subsystem
w ID from serial ROM to distinguish
between different adapters based on
w mthe 21041 chip*
.coProvides PCI clock speed up to
33 MHz, with no wait states on PCI
Umaster operation
et4Enables powerful onchip DMA with
eprogrammable burst sizes up to 32
hlongwords, providing for low CPU
taSImplements unique, patent-pending in-
atelligent arbitration between DMA
channels preventing underflow or
.Doverflow and optimized for full-
wwwduplex operation
Incorporates a 16-bit, general-purpose
Contains two large (256-byte) inde-
pendent receive and transmit FIFOs
Supports either big-endian or little-
endian byte ordering
Implements JTAG compatible test-
access port with boundary-scan pins
Provides full support of IEEE 802.3,
ANSI 8802-3, and Ethernet standards
Offers a unique, patented solution to
Ethernet capture-effect problem
Contains a variety of flexible address
filtering modes
Supports seven LEDs: Receive, Re-
ceive Address Match, Transmit,
Transmit Jabber, Collision, LinkPass,
and Polarity*
Enables automatic detection and cor-
rection of 10BASE-T receive polarity
Enables full autosensing between
10BASE-T, 10BASE2, and 10BASE5
Provides external and internal loop-
back capability
Contains 3.3-V CMOS device which
interfaces to 5.0-V or 3.3-V logic
Provides a software-controllable
power-saving mode*
Supports PCI 5.0-V and 3.3-V signal-
ing environments*
*21041 feature enhancements that are
not available in the 21040.

Digital 21041-PB
Digital Semiconductor 21041 Microarchitecture
The 21041 communicates with the host processor using onchip command and
status registers, and a shared host memory area. Most of the required setup and
initialization is done after power-up. The 21041 software interface and data struc-
tures are optimized to remove load from the host CPU and to allow for maximum
flexibility in the buffers’ descriptor management. In normal operation, very little
host CPU intervention is required. The 21041 filters out runt frames and does not
need to reload the FIFO following collision, thereby minimizing bus traffic.
On the network side, the 21041 provides a direct interface to the AUI and
10BASE-T connections. The 21041 sustains full-line speed reception and trans-
mission. The dual onchip 256-byte FIFOs and the internal microarchitecture pro-
vide complete support for full-duplex operation.
Figure 1 shows the functional groups of the 21041 interface pins.
Figure 1 Digital Semiconductor 21041 Pin Interface
AUI Interface
Twisted−Pair Interface
Boot ROM and LEDs
Digital Semiconductor
PCI Ethernet LAN
PCI Data
PCI Control
MicroWire Serial ROM
System Applications
The 21041 is optimized for PCI-based systems. A direct connection to 10BASE-
T is made through the twisted-pair port. From the AUI port, the 21041 can con-
nect to 10BASE2, 10BASE5, or 10BASE-F using the appropriate media access
unit (MAU) and circuitry. The 21041 is a high- performance, highly integrated
solution for a variety of applications, such as:
Minimum-size, cost-effective PCI-to-Ethernet adapter card
Minimum space, cost-effective integrated PCI motherboard controller
PCI-based, switched Ethernet or multiport Ethernet bridge
Figure 2 shows the PCI-to-Ethernet adapter card using the 21041.
Figure 3 shows the PCI motherboard system with the 21041.
Figure 4 shows the PCI-based bridge and switch using the 21041.

Digital 21041-PB
Figure 2 PCI-to-Ethernet Adapter Card
PCI Bus Connector
Ethernet ID
Digital Semiconductor
PCI Ethernet LAN
Boot ROM
TP Line Driver
Figure 3 PCI Motherboard System
Memory Bus
PCI Slot 0
PCI Slot 1
Digital Semiconductor
PCI Ethernet LAN
Bus Drivers
Video Out

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